One more tang (9k)

[Henk Berends]

Hello all,

There are a few TMS9918A (compatible) rcbus cards already, I built another one using the tang 9k. It can be set to MSX mode or Colecovision mode with a few dip switches and it supports the V9938 80 columns text mode. See attached version 1 schematics.

It works but there are a few possible improvements and enhancements I think.
There's a V9958 32K ram fpga core that I discovered after building the card, it requires A1 on TN 9K pin 16 after studying the schematics in this repo: https://github.com/lfantoniosi/tn_vdp

I'm not a hardware/fpga/AV expert and appreciate your comments:
1. The HDMI port seems to be backpowering the main system. I added a diode to the TN 9K VCC. Would this be sufficient?
2. The HDMI signal doesn't work with all monitors and the 80 columns mode is a bit disappointing i.e. in a smaller window.
   Not sure what to do about that. Maybe this is just a limitation of the FPGA core/firmware which is currently a black box for me.
3. The original design used three 74LVC245AN ic's, I reduced it to two but maybe there's a reason why three are used?
See attached version 2 schematics.

/Henk 

[Mark Durham]

Henk,

Re your Q2, there's a post by Dean Netherton in a discussion I started regarding my RCBus 68000 and his V9958 TN20K where I ask whether it's possible to stretch the active image to fill more of the display surface. Dean went to some length to explain why it wasn't possible. I don't pretend to understand the answer in any detail as I'm not even an FPGA beginner yet.

Mark.

[Dean Netherton]

Hi Henk,

To follow up comments from Mark - I have played a lot with the TN20K module.  I think the code base we have both used for the FPGA, is sourced from the same upstream projects. I cant recall precisely the differences between the implementation of the 9K and 20K - but for the most part, they are the same.  (I think the biggest change the 20K has, is the support for HDMI audio output).  My schematic can be found here: https://www.dinoboards.com.au/assets/hdmi-for-rc/schematic.pdf

So let me share some of my experience - as I think it relates to what you are exploring.  Please note - not an actual electronics engineer -- just a hobbyist - who barely knows what he is doing. 

> 1. The HDMI port seems to be backpowering the main system. I added a diode to the TN 9K VCC. Would this be sufficient? 

I assume you have the "backpowering" issue, when you are reprogramming the Tang Nano module. (I certainty avoid having both TN and the backplane powered at the same time).  For my board, I created jumpers, to allow me to easily disconnect the power line - and also pull the enable pin of the 74LVC245 chips to high - to avoid chance that the buffers and the TangNano both drive pins at the same time - my solution may be overkill and unnecessary.

I suspect the diode would be fine - but I would check a couple of things - the diode will cause a voltage drop to the TangNano, when powered by the backplane - not sure if that will be an issue.  Also - although less of an issue - power can always leak through data lines - full isolation is the less risky, but I have reprogrammed my unit, in circuit, countless times, using just the jumpers mentioned.

> 2. The HDMI signal doesn't work with all monitors...

Hmm.  That interesting... Not sure why you might experience that.  I did have an issue with my Tang Nano 20K version -- when the audio signal is active, some monitors and passive HDMI to DVI converters will not work.  But the TN9K does not have enough power to do the audio - so not sure why you might have issues with some monitors.  Could it be a signal integrity/strength issue?  Have you played with different/shorter cables?  I wonder if this might be an issue with the TN9K hdmi circuit itself.

> 2. ....and the 80 columns mode is a bit disappointing i.e. in a smaller window.

As mark mentioned, I discussed the 'smaller' window issue in his thread.  For the TN20K version, there are 2 HDMI resolutions  576p @ 50Hz and 480p @ 60Hz used.  Its quite a challenge to upscale the 'lower resolutions' of the V9958 to these HDMI modes.  Pixels are doubled - but that still means you get a border.  Are you using a 4:3 monitor or a 16:9 widescreen monitor?

I think there are/were versions of the V9958 emulation, that mapped to 640x480.  This is the absolute lowest resolution that HDMI can support (the V9958's largest progressive resolution is 512x212 - so still short).  What resolution does your monitor indicate it is displaying at?

> 3. The original design used three 74LVC245AN ic's, I reduced it to two but maybe there's a reason why three are used?

Had a look at your 2 schematics.  I do a similar thing for the data bus buffering -- driving the DIR from the /RD signal.  I have not observed any issues.  

I also wondered why others had done it with 2 chips - were they concerned there could be contention (eg: the 74LVC245 driving a line at the same time as the Z80 or the Tang Nano - creating contention).  I cant recall the details now, but I am sure I studied the Z80 timing diagrams and considered how the IOREQ/RD lines become active and confirmed that there is sufficient time and sequence, to ensure the 74LVC245 do not end up driving its output, where it would generate a conflict.

One key difference with my design is I have on-boarded the I/O address decoding to the FPGA chip (that is the 74HCT138 logic is implemented in the FPGA).  I have a pinout on my TangNano called VDP_CS -- this signal is an output, and drives the enable of the buffers.  Moving the address decoding/chip-select to the FPGA gives me 3 key features:

* I can make sure the buffers are only enabled after the data direction has settled (if this proved to be an issue)

* I can change the address the system responds to, by just a quick change of the FPGA code.

* I can later add additional emulated hardware (eg audio chips) - without any hardware updates.

(You will see my design actually uses 3 buffers, despite the consolidation of the data buffer - I need the three buffers as I now need to map all 8 of the Z80's lower address lines).

Hope my notes help.  If there a specific questions as to how/why i did something on my -- happy to try and answer

Cheers

Dean

[Henk Berends]

Hi Dean, Mark,

Thanks for the explanation, the upscaling limitations makes sense.

I tested a few things by rewiring the v1 PCB, it's not that many changes.

1. The backpower is when I have a display attached via the HDMI cable. For reprogramming I just remove the tang from the board. 

Adding the diode seems to eliminate the backpowering. I'll keep it in the v2 design and if it causes a problem replace it with a wire. 

2. The display mode is DVI 640x480 @ 60Hz. I'm using a cheap small chinese brand monitor  4:3 "Eyoyo"  and a 16:9 "Prechen" and  a 16:9 LCD screen from an old laptop with a new circuit board.

The 4:3 Eyoyo doesnt work with any configuration, the Prechen only works with the old F18A core and the LCD screen always works.

The later cores for the tang 9k do support audio, maybe this is the problem with the Prechen. 

I've ordered a HDMI repeater to test with the Eyoyo, maybe this helps.

3. The v2 data line buffer schematics with only one 74LVC245AN works on both my z80 and z180 systems so that's a nice simplification.

I examined your notes and design Dean and I'll probably end up with a TN 20K on one of the systems.

The TN 20K can also emulate the SCC soundchip, it's part of the WonderTang for MSX. That can be a nice addon when playing games.

Btw. the data lines on the tang side are labeled according to TI standards in the days of the TMS9918A meaning that the MSB is bit 0 not bit 7, so this was actually not a mistake in the design.

/Henk