Z80 interrupt priority chain - confusion and questions

[Tom Storey]

I'm second guessing my understanding of the IEI/IEO chain here, wonder if someone can point me in the right direction... Specifically in relation to IM2, and no interrupt nesting (interrupts disabled while in an ISR).

Lets say we have two devices, a CTC with its IEI tied high (so, highest priority device), and an SIO.

The SIO generates an interrupt, and the CPU services it by acquiring its vector and jumping to its ISR.

Lets say the CTC now also generates an interrupt while the CPU is still in the SIO ISR.

Upon exiting the SIO ISR, does the SIO process the RETI, or does the CTC process the RETI because it is the higher priority device asserting an interrupt? Or is it the device that was asserting an interrupt at the time that the vector was acquired that will respond to the RETI?

Furthermore, does anyone know exactly how a lower priority device handles things when it may be in the midst of outputting its vector as part of interrupt acknowledgement and then a higher priority device generates an interrupt?

Im looking at the "THE Z80 FAMILY PROGRAM INTERRUPT STRUCTURE" document which has some example interrupt control logic, although I suspect this is very basic logic - I laid it out in logicly (simulation app) and have found one flaw so far, but also I am trying to determine how a lower priority device should handle being interrupted by a higher priority device.

So far it would seem with the logic from that document alone, the lower priority devices interrupt would essentially be lost - it doesn't have a mechanism to ensure that it successfully completes an interrupt in full, and I've been playing around trying to figure out a way to implement such a feature.

[Tom Storey]

As always seems to be the case when I post an email (if not while writing it) about something, I tend to discover the answer. It was "hiding" on a much earlier page (10) in the last paragraph.

Think pretty much everyone can ignore this. :-P