Help with first Z80 design

[Enaiel]

Hi all,

First post here. I'm trying to design my first Z80 SBC. This is just my 3rd ever PCB design, so I'm a total noob at this. I started with Grant Searle's design and added support for 512K banked RAM and ROM. In the spirit of Grant's minimal component design, I came up with a simple banking scheme: memory is divided into 32 32K pages. Pages 0-15 come from ROM, while pages 16-31 come from RAM. Page 31 is permanently mapped to upper 32K memory segment 8000-FFFF, while any page from 0-31 can be mapped to lower 32K memory segment 0000-7FFF. Changing the bank requires a write to a single port, since the first 3 bits will set the bank, while bit 4 will select ROM or RAM. On reset, bank 0 will be selected, which will also automatically select the ROM.

According to my total noob brain, this scheme should work. Is there a memory manager in RomWBW that supports such a scheme? Or do I need to redesign it to be more like N8VEM (https://retrobrewcomputers.org/n8vem-pbwiki-archive/0/35845334/48860639/35845544/MPCL_V2.txt) for it to be compatible with RomWBW?

Thanks,
-Enaiel   

[Enaiel]

> Changing the bank requires a write to a single port, since the first 3 bits will set the bank, while bit 4 will select ROM or RAM. 

Meant to write bits 0-3 and not first 3 bits obviously, but my brain can't count from zero :)

[Steve Cousins]

Hi Enaiel   

You asked: "Is there a memory manager in RomWBW that supports such a scheme?"

Nearly. The existing MM_Z2 driver in RomWBW requires the bank select bits to be shifted by 1 bit to allow for MM_Z2's assumption that 16k banks are used (in pairs). So change the '174 inputs from D0-4 to D1-5. ie. pin 3 is D1, pin 4 is D2, etc.

I have implemented this scheme in my design SC714 (RCBus module). I used a 74HCT157and 74AHCT139 rather than OR gates but that's not significant to the MM_Z2 driver. 

I also use this scheme in my designs SC602 (RCBus module) and SC720 (SBC). These designs have the option of two ROMs (switch selectable) but again that is not significant to the MM_Z2 driver.

Steve

[Enaiel]

Hi Steve

That's interesting. I was wondering how the MM_Z2 driver was working with your designs. Thanks for the explanation!

So it's either make this change, or connect D7 to '174 pin 13 instead of connecting D4, and use the MM_SBC driver? Are these my best options?

Thanks,

-Enaiel

[Mark T]

I have been thinking of a minimum implementation for an SBC or slave board, only 128k RAM and 256k Flash.

A few cheats here:

74HCT173 requires a positive logic reset, but might get away with an RC circuit to provide this on the rising edge of reset if there is no spare inverter available..

IO address is not decoded, this would have multiple shadows through address range. Its likely any SBC would need other IO addresses decoded with a 74hct138, but could also use a single address line low for each IO device and avoid the overlapping addresses.

[Enaiel]

Hi Mark,

That's super interesting - no gates required! What is A1 and PAGE used for?

Thanks,

-Enaiel

[Jaap van Ganswijk]

Why not use a Z180, Z280 or Z380? What is your goal? Do you want to run a serious OS like Unix? Then you need to have two states of the CPU: One for  the OS and one for the user software. Not easy with a real Z80, but we did it with a 6809 in the late 1980's: see: http://idd.nl/sophie. Was not perfect though...

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[Enaiel]

I guess the question is why Z80?

* Nostalgia, my first computer was a ZX Spectrum.
* Re-live the homebrew microcomputer revolution with Z80 + BASIC, CP/M.
* ColecoVision, SG-1000 and MSX can be built with off-the-shelf components..

Being a total noob, the goals for this Z80 SBC are:

* Start with the simplest established circuit that runs BASIC and CP/M: Grant Searle's CP/M on breadboard.
* Extend it to support 512K banked RAM and ROM and make it compatible with RomWBW.
* Limit design to 100mmx100mm 2-layer PCB with through-the-hole components.
* Provide expandability with a RC2014 bus to leverage the many RC2014 expansions available online.
* ???
* Profit?

Here's my full design for the board. Looking for tips on the best way to make it compatible with RomWBW.

[Alan Cox]

IO address is not decoded, this would have multiple shadows through address range. Its likely any SBC would need other IO addresses decoded with a 74hct138, but could also use a single address line low for each IO device and avoid the overlapping addresses.

That only really works with NMOS. It was done on the old micros because all the devices were NMOS so multiple chip select 'accidents' caused totem pole behaviour not fried chips. It's not a good idea with CMOS, and actually causes problems if you replace NMOS with CMOS in those systems. 

I did look at various minimal 128K RAM systems but after the Simple80 I gave up because Bill had won the game.

Alan

[Mark T]

A1 is used for partial IO addressing, leaves a lot of overlap with other IO ports. As Alan noted, not a good idea in cmos systems, though this is output port only so shouldn’t be a big problem, but blocks a lot of the IO address spaces.

Page is a control line on RCBus used to control pageable RAM from Pageable ROM boards. Driving that might allow the use of the Pageable ROM board with 128k RAM, if the address decoding on the Pageable ROM board is removed. Plan is to use this for an FT245 to bootstrap battery backed RAM by providing a stream of z80 instructions over usb to initialise RAM. This is a simpler version of a previous project that read all instructions from FT245 for bootstrap.

[Mark T]

Hi Enaiel

It looks like you swapped ROM_CS and RAM_CS on the memory. 

You don’t really need MEMRD and MEMWR on the memory, just use RD and WR direct from the z80, the chip selects are already dependent on MREQ.

There have been a few variations of the compact flash interface, maybe check the latest design by Tadeus with some improvements to the timing to work with a larger number of compact flash modules.

Mark

[Enaiel]

Hi Mark

> It looks like you swapped ROM_CS and RAM_CS on the memory.

Ooops! Thanks for catching that!

> You don’t really need MEMRD and MEMWR on the memory, just use RD and WR direct from the z80, the chip selects are already dependent on MREQ.

Right, that would save 2 gates.

> There have been a few variations of the compact flash interface, maybe check the latest design by Tadeus with some improvements to the timing to work with a larger number of compact flash modules.

I see, but I don't have space on the PCB for the additional '138 and '74 chips, so I'll just have to live with a worse implementation.

Thanks so much for your help!

-Enaiel

[Wayne Warthen]

Sorry I'm a bit late to the party, but I wanted to respond to the questions related to RomWBW.

The proposed bank selection port bit layout seems to be:

---RNNNN

where R=1 for RAM and R=0 for ROM.  The N bits just select the bank within ROM or RAM.

It does not exactly match any of the existing designs for selecting banks, but the work to implement this would be 3-4 lines of assembler.  RomWBW can be adapted to this design very easily.

Internally, RomWBW uses the following bit layout for bank selection:

RNNNNNNN

So, if you wanted to make bank switching as fast as possible in RomWBW, you could change your bank selection port bit layout to:

R---NNNN

which would allow RomWBW to perform a bank selection with no translation at all.

Thanks, Wayne

[Enaiel]

Hi Wayne

For the  R---NNNN bank selection port bit layout, what memory manager would I need to choose? 

MM_SBC? And MPCL_RAM and MPCL_ROM can use the same address?

Thanks,

-Enaiel

[Wayne Warthen]

On Monday, February 17, 2025 at 1:50:38 PM UTC-8 ena...@gmail.com wrote:

For the  R---NNNN bank selection port bit layout, what memory manager would I need to choose? 

MM_SBC? And MPCL_RAM and MPCL_ROM can use the same address?

Yes, using the MM_SBC memory manager w/  MPCL_RAM and MPCL_ROM set to the same address would work fine for R---NNNN.  That would allow you to bring up your board with the existing RomWBW codebase.

Ultimately, I would create a new memory manager for you that is more optimized by avoiding the second port I/O.

Thanks, Wayne

[Mark T]

Hi Wayne,

Spencer’s 512k ROM/RAM module and Steve’s designs all use D5 for ROM/RAM selection. 

(Watch out for the pin out error in Spencer’s schematic that still hasn’t been fixed.)

Do they have an address translation in their version of ROMWBW? I thought they used the default build.

Mark

On Monday, February 17, 2025 at 2:07:20 PM UTC-5 Wayne Warthen wrote:

[Wayne Warthen]

On Monday, February 17, 2025 at 4:36:54 PM UTC-8 Mark T wrote:

Spencer’s 512k ROM/RAM module and Steve’s designs all use D5 for ROM/RAM selection. 

(Watch out for the pin out error in Spencer’s schematic that still hasn’t been fixed.)

Yes, you are correct.  The reason that D5 is used (instead of D4 as discussed above) is because the Zeta 2 memory management scheme actually implements 16K banks.  As a result, the RAM/ROM toggle bit is one bit position higher.

Do they have an address translation in their version of ROMWBW? I thought they used the default build. 

I'm not sure what you mean by default build...  All RomWBW adaptations have a memory manager.  The Zeta 2 memory management (used by Spencer and Steve) uses a translation that winds up doing 2 I/Os to set 2 16K banks to achieve the 32K bank switching needed by RomWBW.  Steve's specific implementation is a little hard to explain.  It actually does use a 32K bank, but is compatible with the Zeta 2 translation.  It would be possible to create a specific memory manager for Steve's design that is a bit more optimized.

Thanks, Wayne

[Mark T]

I was considering the zeta 2 memory manager as the default, maybe just most common due to RC2014 using this.

———RNNNN for zeta 2 memory manager 16k pages

———RNNN— for Steve’s implementation for 32k pages, which is compatible with zeta 2 if writes to port ——————1– are ignored by hardware.

Would R————NNN be the optimum format for internal memory management of ROMWBW ?

[Mark T]

Missed a bit, should be

——RNNNNN for zeta 2 memory manager 16k pages

——RNNNN— for Steve’s implementation for 32k pages, which is compatible with zeta 2 if writes to port ——————1– are ignored by hardware.

Would R———NNNN be the optimum format for internal memory management of ROMWBW ?

[Bill Shen]

 

RomWBW bank register interface is consolidated in one location with just few lines of code, so it is easy to modify.  I’ve probably caused more headaches for Wayne Warthen with my spur-of-moment banking schemes, but he has managed to accommodate them all gracefully.  Eazy80 is RN—-NNN, ZRC is R-NNNNNN, ZRC-SIMM is NNNNNNNN.  I have just ported RomWBW to Z80retro which is NNNN——.  They are all over the map, but easily accommodate by RomWBW.

Bill 

[Jaap van Ganswijk]

The Z180, Z280, Z380 and HD64180 contain a complete Z80 and much more like 2 uarts in the 180's and even  memory controller in the 280 and probably the 380 too. Look for the SC131 SBC board and others. You can buy them on Ebay. Also see scc.me.uk.

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[Wayne Warthen]

On Monday, February 17, 2025 at 8:10:56 PM UTC-8 Mark T wrote:

Missed a bit, should be

——RNNNNN for zeta 2 memory manager 16k pages

——RNNNN— for Steve’s implementation for 32k pages, which is compatible with zeta 2 if writes to port ——————1– are ignored by hardware.

Would R———NNNN be the optimum format for internal memory management of ROMWBW ?

Yes.  Well, actually, the "native" RomWBW bank selection byte is RNNNINNNN.  However, the higher order N's really don't matter when the system does not have enough RAM/ROM for them to be relevant.

The use of that format sill result in no translation which slightly improves the bank selection speed.  It does matter though because RomWBW does a LOT of bank selection since every API call does that.

[Wayne Warthen]

On Tuesday, February 18, 2025 at 10:24:23 AM UTC-8 Wayne Warthen wrote:

Yes.  Well, actually, the "native" RomWBW bank selection byte is RNNNINNNN.  However, the higher order N's really don't matter when the system does not have enough RAM/ROM for them to be relevant.

RNNNINNNN should have been RNNNNNNN.  There is no "I" in there.

-Wayne 

[Enaiel]

Hi Wayne

> Yes, using the MM_SBC memory manager w/  MPCL_RAM and MPCL_ROM set to the same address would work fine for R---NNNN.  That would allow you to bring up your board with the existing RomWBW codebase.

I was able to compile and build a ROM image with this configuration, Now to actually build the board and test it out.

>  Ultimately, I would create a new memory manager for you that is more optimized by avoiding the second port I/O.

That would be really awesome!

Thanks,

-Enaiel

[Enaiel]

Hi all

I'm back to this project after a 1 year break due to tariffs. After reviewing my schematics, I realized that many of the KiCad symbols I downloaded from the internet have incorrectly numbered pins. Does anyone have a KiCad symbol library with one or more of the following ICs that they can share?

* Z80CPU
* AS6C4008
* SST39SF040
* Z80SIO/O
* DS1233

Additionally, a KiCad symbol for RCBus would be much appreciated.

Thanks,
-Enaiel

[7alken]

hi Enaiel, try to peek there for Johs schematics and boards also ...  we used all these;
https://github.com/Z80-Retro/2063-Z80
https://github.com/Z80-Retro

P.

[Enaiel]

Thanks 7alken and Ed Silky for your help. I scoured through GitHub and cross-referenced datasheets to fix my symbols. I obsessively refined my design for a year due to tariffs. I'm think I'm finally ready to send it for production. I just have 20 ""Thermal relief connection to zone incomplete" errors to fix in KiCad before I send it. Any tips on how to fix these quickly?

Regards,

-Enaiel 

On Tuesday, January 27, 2026 at 9:18:40 PM UTC-5 7alken wrote:

hi Enaiel, try to peek there for Johs schematics and boards also ...  we used all these;
https://github.com/Z80-Retro/2063-Z80
https://github.com/Z80-Retro

P.

[Doug Jackson]

They are a standard error.  I have never bothered to rectify them, because in every case, it's because I have routed near the pin and I need the signal.

Doug.

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[Enaiel]

Oh, really? I have been painstakingly trying to fix them by moving traces and rotating spokes!

On Saturday, January 31, 2026 at 12:29:31 AM UTC-5 Doug wrote:

They are a standard error.  I have never bothered to rectify them, because in every case, it's because I have routed near the pin and I need the signal.

Doug.

[Sergey Kiselev]

Looks like I am very late to the party :)

In many years I've been using KiCad I never seen that error... So it must be something relatively new.

It appears to be related to the number of the thermal relief "spokes" that connect a pad to the rest of the zone.

Ideally it should be 2 or more e.g., to ensure good ground/power connection, and that's the DRC default. It can be changed here:

https://forum.kicad.info/t/ground-plane-error-thermal-relief-connection-to-zone-incomplete/41191

My KiCad symbols, should contain most of the symbols you need:

https://github.com/skiselev/my_kicad_library

My simple Z80 RCBus Z80 CPU + Paged memory project. Implements Steve's idea of minimal Zeta SBC V2 compatible, from RomWBW perspective, memory pager: 

https://github.com/skiselev/z80-cpm

[Enaiel]

Hi Sergey

I managed to fix my symbols, but thanks so much for your symbol library. I'm sure it will come useful.

Yeah, the KiCad error is probably new. I will try to fix as many as I can, and ignore the rest.

Your Z80-CPM project is really interesting. You have so many interesting projects! Omega, in particular has been a huge inspiration. I came up with my own memory banking scheme. Would really appreciate if you can review my final circuit design before I send it out for production.   

Thanks,

-Enaiel 

[Mark T]

I think U9A should change from NOR to OR, to clock data at the end of the Write cycle.

U11B doesn’t need to be an inverter, so you could use that for U9B.

Then you can remove the 4 NOR gates and reduce the chip count.

[Sergey Kiselev]

Looks like I forgot to copy the group. Enaiel, apologies for another email...

I recommend using an oscillator instead of the crystal + logic gates. These oscillator circuits tend to be finicky, and sensitive to the layout, noise, and components selection. It is more stable, easier to change the frequency if you put it in a socket, and requires less components and board space.

It appears that Grant's circuit gets copied over and over... 

You qualify the memory /RD and /WR signals twice with /MREQ - once using U6A and U6B, and the second time using U10B and U10C. No need to do that. You'll save a 74HCT32 IC, and reduce the latency.

It is preferable to qualify RAM and ROM /CS with the /MREQ (that's what you are doing with U10B and U10C, not the /RD and /WR. This leaves the memory in the power saving state...

Is the /CTSB intentionally omitted from J3? I'd route it anyway. Then, you just can skip the resistor if you don't want a connection.

Regarding the CF interface. The naive implementation that Grant has and RC2014 initially copied doesn't work well with many CF cards due to the timing issues. Tadeusz did a redesign, that works better: https://github.com/tpycio/CFModule

You can use a resistor network instead of R1-R5, that would save some board real estate.

Also, it might be a good idea to have a 10k or so pull-up resistors on the data bus.

Add a larger capacitor - 47uF or so, where power supply connects, e.g., by the USB connector.

Also, since you're going with a Micro USB connector, one idea would be to add an FT231 USB to Serial IC, and have a console on that USB port...

I agree with Mark, that U9A should be an OR gate.

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[Enaiel]

Hi Sergey

 

My goal was to design and build the easiest and cheapest possible Z80 SBC that can run CP/M and RomWBW. That means doing a minimal chip count design with THT components on a 100mm board, and buying components from Aliexpress..  

I recommend using an oscillator instead of the crystal + logic gates. These oscillator circuits tend to be finicky, and sensitive to the layout, noise, and components selection. It is more stable, easier to change the frequency if you put it in a socket, and requires less components and board space.

I agree about using oscillators, but they are hard to find from cheap Chinese sellers.

 

It appears that Grant's circuit gets copied over and over... 

Grant's circuit was the starting point of this design too :)

 

You qualify the memory /RD and /WR signals twice with /MREQ - once using U6A and U6B, and the second time using U10B and U10C. No need to do that. You'll save a 74HCT32 IC, and reduce the latency.<

It is preferable to qualify RAM and ROM /CS with the /MREQ (that's what you are doing with U10B and U10C, not the /RD and /WR. This leaves the memory in the power saving state...

Thanks, I believe Mark had suggested this earlier as well. Done.

 

Is the /CTSB intentionally omitted from J3? I'd route it anyway. Then, you just can skip the resistor if you don't want a connection.

Yes, so I can plug in the cheap FTDI boards from Aliexpress that have DTR instead of CTS. If I route it, wouldn't it need to be grounded if I don't use it? . 

 

Regarding the CF interface. The naive implementation that Grant has and RC2014 initially copied doesn't work well with many CF cards due to the timing issues. Tadeusz did a redesign, that works better: https://github.com/tpycio/CFModule

Yes, this too was suggested by Mark, but I didn't have space on the board. I added the 100 ohm resistor and 100 pf capacitor for a unbuffered solution. Also, doesn't the buffered version have trouble with CF-SD adapters?

 

You can use a resistor network instead of R1-R5, that would save some board real estate.

Also, it might be a good idea to have a 10k or so pull-up resistors on the data bus.

Agreed on both, but I'm staying away from resistor networks to keep costs down.

 

Add a larger capacitor - 47uF or so, where power supply connects, e.g., by the USB connector.

Great idea, done.

 

Also, since you're going with a Micro USB connector, one idea would be to add an FT231 USB to Serial IC, and have a console on that USB port...

I'm using a Micro USB breakout board, so it's still THT. 

I agree with Mark, that U9A should be an OR gate.

Great, made this change, but not sure how it works? I would think that the 174 would then get clocked when either MEM_CS or IOWR were not active? Versus when both MEM_CS and IOWR were active.

Thanks so much to both you  and Mark for your advice. I have so much to learn!

Regards,

-Enaiel 

[Mark T]

“Great, made this change, but not sure how it works? I would think that the 174 would then get clocked when either MEM_CS or IOWR were not active? Versus when both MEM_CS and IOWR were active.”

OR gate output goes low only when both MEM_CS and IOWR are both low, then when either of these goes high the output will return high, giving a positive edge to clock the 174 at the end of the output cycle.

[Bill Shen]

For a low-cost, through-hole design, you may be interested in Eazy80.  It was designed with the low-cost kit from China in mind (the kit is $7.50 but shipping is expensive; you can buy multiple kits with the same shipping cost, however).  The basic Eazy80 kit has no glue logic and is CP/M capable.  For RomWBW capability, replace the original 128K RAM with 512K RAM and add a quad OR gate.  Assuming the kit is shipped with CMOS Z80 (most of the time), it is capable of 22MHz operation.  I believe it can be packed into a standard RC2014 form factor (50mmX100mm), but KIO has so many I/O features (it is a superIO combination of SIO, PIO, CTC) that I want to have a breadboard area to experiment with.  That's why my current implementation is 100mmX100mm with a large prototype area.   Because of low cost and large prototype area, this is becoming my favorite Z80 experimentation SBC.
Eazy80 rev1 design files are here, but because of bots the retrobrewcomputers site is almost inaccessible now.  I'm trying to relocate my designs to GitHub, but that'll take months.
Bill

[Mark T]

I thought most people were moving away from github due to AI.

The problems with retrobrewcomputers is probably due to AI bots, don’t encourage them by using sites that use AI.

[Alan Cox]

On Sun, 1 Feb 2026 at 17:22, Mark T <mark...@gmail.com> wrote:

I thought most people were moving away from github due to AI.

Also because of random account bans and spurious takedowns.

Fuzix has moved to Codeberg for those reasons and AI.

I did find Grant's design somewhat convoluted and missing a few tricks although I'm not 100% sure that Bill's Simple80 isn't take it to the other extreme - but it does work nicely.

I've generally avoided crystals and gone with can oscillators. The less things that can go mysteriously wrong in a new board design the better.

[Bill Shen]

I’m an old man so I don’t really care if AI steals my designs.  It is more important that the designs are accessible and the hosting site is not shut out by bots.  Small hosts like retrobrewcomputers probably won’t survive long.

[Enaiel]

Hi Bill

On Sunday, February 1, 2026 at 8:02:07 AM UTC-5 Bill Shen wrote:

For a low-cost, through-hole design, you may be interested in Eazy80.  

That's a really interesting project, but as Alan says, probably too far removed from my Grant Searle inspired design.

 Thanks,

-Enaiel

[Enaiel]

Hi Mark

OR gate output goes low only when both MEM_CS and IOWR are both low, then when either of these goes high the output will return high, giving a positive edge to clock the 174 at the end of the output cycle.

Thank you so much for the explanation.

 

From Sergey's comments, I have two open questions:

1. I intentionally omitted CTSB from J3 so that I can plug in the cheap FTDI boards from Aliexpress that have DTR instead of CTS. If I route it as Sergey suggested, wouldn't I need to ground CTS if I don't use it? 

2. Both you and Sergey mentioned I should use Tadeusz design for the CF interface. Does his buffered interface work with CF-SD adapters, as CF cards are getting rare?

Thanks again for all your help.

-Enaiel

[Mark T]

Small hosts will probably last longer if we don’t provide support to sites using AI.

It seems that AI bots are deliberately being used to make these smaller sites unuseable.

[Mark T]

The other problem with FTDI is if they are based on clones the drivers may brick the adapter. I changed to using CH340 adapters instead. Some adapters have a link to select between DTR and CTS.

If you intend to use SD cards then consider putting an SD card interface on your board instead. Check Steve Cousins small computer projects for a bit banged SD interface supported by ROMWBW.

[Tadeusz Pycio]

Hi Enaiel

2. Both you and Sergey mentioned I should use Tadeusz design for the CF interface. Does his buffered interface work with CF-SD adapters, as CF cards are getting rare?

The main reason for creating this CF interface was precisely such an SD to CF adapter. I came across an exceptionally temperamental one, and that motivated me to solve this problem. The performance of disk operations using this interface is the highest among the available solutions. 

[Enaiel]

Hi Tadeusz

I thought your design was buffered with a 245, but this looks unbuffered. So what changes do I have to make to my circuit? Bear in mind I only have space for at most one more IC on my 100mm board.

Thanks,

-Enaiel