Thanks guys. Let me tell you more about my situation.
As you probably know, after a three year hiatus I and working again the Interocitor. The Front Panel takes control of the system using BUSREQ. When I get the BUSACK the bus is up for grabs. In my design, I do not touch any circuits at all except BUSREQ.
I have added numbers so I can track my action items.
(1) Mark T, I am beginning to think that CPU control signals should be held (inactive) except when needed. This might actually be the case in my design, but if it is, it's by happenstance (luck). :::> Check this.
(2) Alan, regarding the address and data lines. On the data bus side, I suspect they can be left open and I will get, as Mark says, the byte FFh. Which is fine. Regarding addresses though, my Font Panel can address only the first 256 bytes, so all addressing is limited to 0000h - 00FFh. And RAM, for me, begins at 0000h. That means the high order address lines must be low. The Front Panel does nothing with A15-A8 which means it will probably not be accessing low memory. I guess this depends on the memory chips involved . :::> The high order bits will need to be kept low. I will look at doing this on one the Interocitor cards.
(3) My question was originally posed because I have latches reading the address bus. So I am examining what happens if an HCT latch has an open input, that is, the latch input is looking at a tri-stated output. Not good, I think. :::> review
(4) It might be simpler from a design perspective up put pull-up /pull-downs on the motherboard. The way I would not have to track wether a signal was tri-state mode. :::> See if anyone has already tried this.
(5) It seems to me that the control inputs MUST be controlled at all times. They continue to function during a BUSACK. I should go through the control signals one at a time. :::> review Zilog spec.
You see things when you leave a project and then come back to it later.