68K 16-bit Wide EPROM

[Tom Szolyga]

I want to build a firmware board for the 68K using a M27C322 which is a 2Mx16 EPROM.  The 68K has upper and lower data strobe signals.  That makes it easy to enable two 8-bit wide EPROMs.  The question is how to combine them for a 16-bit enable.  Also, when the 68K does a byte read or write, what happens to the other byte in the 16 bit word?

OR

Is the whole idea not doable?  

Best regards,

Tom

[Sergey Kiselev]

Unless you're planning to program that 16-bit EPROM in the system (unlikely), write support is not relevant. When doing byte reads, CPU is going to ignore the data on not relevant part of the data bus.

Therefore, you can logic AND (negative logic OR) /UDS and /LDS together, OR (negative logic AND) that with negated R/W signal, and address decoder output.

I think the resulting logic equation is going to look like this:

/E = (/UDS and /LDS) or (not R/W) or (/ROMCS)

Where /ROMCS is the output of your address decoder.

-SK

[Bill Shen]

Tom,
A simplistic design is connect 27C322 A0:A20 to 68000's A1:A21 and connect 68000 A22 OR'ed with 68000 address strobe to 27C322's enable, ignoring UDS and LDS completely. This is read-only so valid data is always present on D0:D15, 68000 will read in the correct data regardless of word, odd byte or even byte read. You can include the R/W signal in decoding logic to avoid data contention if 68000 is writing to 27C322 space.

Since 68000's exception vector is fixed at 0x0-0x3FF, the A22 line should go thru a XOR gate driven by a paging flipflop so you can switch 0-3FF between RAM/ROM.
Bill

[Tom Storey]

You could use a pair of '245's or similar to provide byte wise tri-stating between the ROM and the data bus? 

[Tom Szolyga]

Thanks guys!  A single EPROM, x16 organization, It looks very doable. I will start on the schematic.

Tom 

[Steve Crompton]

Hello Tom,

Using the 27C322 should be pretty easy - invert the 68000's R/W line and connect the inverted R/W line to the OE or G pin, The CS or E pin on the 27C322 should be driven from the address decoding logic but gated with the 68000's AS in the usual way. All 16 bits will be placed on the bus for the 68000 to read either the upper 8 bits or the lower 8 bits, UDS and LDS are not required, the 68000 will take either the upper or lower 8 bits as necessary. Note: you cannot apply this method for 16 bit wide RAM though because the 68000 may need to write bytes at a time not words at a time, but for ROM its fine as it is read only. 

Best Regards

Steve