Clock distribution

[Tadeusz Pycio]

I'm starting to catch up, at the beginning my Z280 project returned. I have a question which way of distributing the clock seems more correct to you? If you see other errors then comments are welcome, this scheme is today's reflection, concept.

[Tom Storey]

What is the purpose of having the ATtiny in the circuit?

Either of them is likely just fine, but it depends on what exactly you want to achieve.

On Sat, Apr 4, 2020, 22:50 Tadeusz Pycio <ta...@wp.pl> wrote:

I'm starting to catch up, at the beginning my Z280 project returned. I have a question which way of distributing the clock seems more correct to you? If you see other errors then comments are welcome, this scheme is today's reflection, concept.

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[Tadeusz Pycio]

What is the purpose of having the ATtiny in the circuit?

Hi, Tom

ATtiny controls and loads from the internal EEPROM boostrap (small boot loader) for Z280. Such a system does not need a ROM, and AVR is definitely a smaller integrated circuit. After the boot process, it will do nothing. Bill Shen in his design uses a serial loader from PC or like in Z280RC using CPLD glue logic. The solution with AVR is another way.

[Greg Holdren]

Tadeusz,

Bill actually uses the built-in boot strap mode that the Z280 provides on at least the ZZ80RC and CF boards. The CPLDs emulate what the Z280 based board are doing on his Z80 designs.

Greg

[Bill Shen]

Tadeusz,
The values of AD0-7 and nWAIT signals at the negation of RESET determine how Z280 will boot.  Are you forcing Z280 into serial bootstrap mode and then feed the Z280's serial-in with ATtiny's serial-out data?  I assume ATtiny's serial output can be tri-stated so not to interfere with normal serial communication?  The serial bootstrap code is limited to 256 bytes, so how you plan to load more data? 
  Bill

[Tadeusz Pycio]

Hi, Bill

This is exactly how it should be. ATtiny sets the bootstrap mode, loads the boot loader (which assumes the existence of CF mass storage at address 0x10), then sets its ports to input mode. Pin 2 AVR (RX) during the boot process is the I/O port that controls the state of the TX Z280 line, the diagram may be misleading. Ultimately, I plan to use DIP14 - ATtiny84A, I prefer to do the experimental version with AVR which has hardware UART. I purposely used microcontrollers that have >256 bytes of EEPROM to easily change the Z280 loader without interfering with the AVR program. The ATtiny counter also generates the XTAL/10 serial transmission clock

[Tadeusz Pycio]

Bill actually uses the built-in boot strap mode that the Z280 provides on at least the ZZ80RC and CF boards. The CPLDs emulate what the Z280 based board are doing on his Z80 designs.

 

Hi, Greg

After a moment's thought, is CF @ 0x10 necessary in my project? The loader can load the rest of the program through the serial port. I will think about how to connect a larger external EEPROM to AVR.

[Bill Shen]

Great, that should work well.

Since the hardware is always connected to a terminal such as TeraTerm on Windows PC, an alternative approach is to make the terminal "smart" to take care of the serial loading automatically.  For an example, TeraTerm has powerful macro capability, so it is possible to load the 256-byte bootstrap and load applications with one macro command.  At 115200 baud, the loading process can be very quick depending on the size of the applications.

I thought about a custom software that'll automatically load the bootstrap and specified application whenever the hardware powered up, but I'm not good with Windows software.
  Bill

[Tadeusz Pycio]

Hi, Bill

The question about mass storage gave me the idea to use the UART Z280 only for communication with AVR. This will allow the use of existing SIO and ACIA modules as terminal ports, mass storage does not need to have ROM content. I think to use ATtiny as a Serial bridge to I2C.
Do I need to map the entire Bus Timing and Initialization Register in the bootsrap process?

[Bill Shen]

Hi Tadeusz,

Z280 UART is very robust, supported by two DMA channels, so booting out of the UART and using it as high speed communication channel to other processor(s) are well within its capability.

You need to set AD0, 1, 6, 7 at reset to set the bus speed and bootstrap mode. The other options can be set in software. The Z280 document is conflicted about AD7, it must be 0 at reset to load the initialization register correctly. I figured that out by trial-and-error.
Bill

[Bill Shen]

It is interesting to think about a cluster of Z280 using the UART as high speed communication backbone. One master as the I/O processor that serially bootstrap all the remaining Z280 and handle IO requests over the UART bus. It is possible to build compact multiprocessing Z280 on a RC2014 backplane.
Bill

[Greg Holdren]

I was just mentioning some of the Z280 boards that Bill made that I have which have no CPLDs. One has no CF, ZZ80RC and a ZZ80CF which has CF. I wasn't really talking about mass storage. I wasn't clear enough. :)

Greg

[Bill Shen]

I have tried several bootstrap methods with Z280. I think they all have 2 modes of operations controlled by jumper selects; one of the mode is always bootstrap from UART. The second mode may be from battery-backed RAM, or from CF disk, or from EPROM. The deciding factor is whether they have CPLD. The latest design is all through-hole technology, no CPLD, no battery-back and no EPROM programmer.
Bill

[Tadeusz Pycio]

I've been looking for this old thread for a long time and it looks like after 3 years the idea has finally come to fruition. I am currently working on the control software, currently only the clock distribution and reset control are working. I hope the whole thing makes sense and also the bootstrap will work.

[Tadeusz Pycio]

Today I had a chance to work with the software for the AVR controlling the Z280 processor. The distribution of clocks (system clock and CTIN0 for the serial port) and the setting of the control register to get the clock on the bus compatible with the processor's internal clock are now working. The part that remains to be run is checking the state of the BOOT jumper and loading the serial bootstrap sequence from the internal EEPROM.
Module unfortunately to be fixed, I left the RDY inputs hanging ...

[Tadeusz Pycio]

Module unfortunately to be fixed, I left the RDY inputs hanging ...

Well... I did a patch version after a long break and made another mistake related to the DMA channels. I have a lesson that corrections should be done on the fly and not after such a long time.
Yes I pulled up the /RDY inputs, but all of them which resulted in not being able to use the DMA0 and DMA1 channels via software ( I don't know why the software RDY bit is connected to the /RDY input with an OR function, which is what Zilog wanted to achieve this way ?). It is obvious that the /RDY inputs for the DMA2 and DMA3 channels should be pulled up when connected to the RCBus so that the devices can report a service request. This is where I question whether there should also be an option to force a LOW state on the /RDY inputs of the higher DMA channels when linking DMA channels (DMA0 with DMA2 and DMA1 with DMA3)? Does anyone have experience of this, as the documentation is silent on this issue ( unless I should treat this as a standalone DMA channel )? Yes an option is to add a jumper. I'm angry at myself for forgetting about software support for DMA channels 0 and 1.

[Tadeusz Pycio]

I am slowly managing to master the Z280, the module already allows loading the operating system from the CF with the help of a serial bootstrap routine contained in the microcontroller's EEPROM (the rom-less system is very convenient, as you don't have to reprogram the flash). Currently I already have CP/M 2.2 and a basic version of MP/M running (still without bank memory and interrupt-based console).
Attached is a short video showing the process of booting the CP/M operating system and then MP/M.

[Tadeusz Pycio]

"The Interrupt/Trap Vector Table must start on a 4K byte boundary in physical memory (that is, a memory address whose 12 least significant bits are all zeros)."

Momentarily, my work on MP/M for the Z280 has unexpectedly come to a halt, as I have no idea how to elegantly resolve this while merging the OS kernel modules. I need to think more deeply about solving this problem without resorting to magic software tricks.

[Fred Weigel]

No tricks, may be magic:

  ds 4096

fourk:

 ds 4096

lxi h,fourk

mvi l,0

mov a,h

ani 0f0h

mov h,a

; use hl as 4k aligned interrupt table

[Tadeusz Pycio]

Yes, you are right, that is a good solution. Thank you, I have already overcome this obstacle. I wanted to solve this problem in the classic Z80 way, which was a big mistake. On the Z280 I have an advanced MMU and each MP/M bank has 5 free blocks of 4kB each, so I even have an excess of available space to create this array. Sometimes you don't see the obvious.

[Tom Storey]

Does your assembler have any concept of alignment for labels? Most of them tend to. You should simply be able to specify that you want the label for the IVT aligned to 4096 bytes and it'll take care of the rest.

On Thu, 2 Nov 2023, 01:35 Tadeusz Pycio, <ta...@wp.pl> wrote:

Yes, you are right, that is a good solution. Thank you, I have already overcome this obstacle. I wanted to solve this problem in the classic Z80 way, which was a big mistake. On the Z280 I have an advanced MMU and each MP/M bank has 5 free blocks of 4kB each, so I even have an excess of available space to create this array. Sometimes you don't see the obvious.

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[Tadeusz Pycio]

Hi Tom,

This will work at the level of the XIOS module over which I have control, but in the course of linking kernel modules the relative address may change, as I am unable to determine the lengths preceding my module which are included in the kernel. All kernel modules must be relocatable and explicit, absolute addresses are not allowed there. Fortunately, the Z280 specifies the location of the interrupt jump table in any 16MB physical memory location, so I just need to ensure that it is unused and starts at the 4kB block boundary. The interrupt service routines must be in the logical 64kB space supported by the processor, and there is no such problem here.

[Tom Storey]

Ah ok. Got it.

On Thu, 2 Nov 2023, 12:47 Tadeusz Pycio, <ta...@wp.pl> wrote:

Hi Tom,

This will work at the level of the XIOS module over which I have control, but in the course of linking kernel modules the relative address may change, as I am unable to determine the lengths preceding my module which are included in the kernel. All kernel modules must be relocatable and explicit, absolute addresses are not allowed there. Fortunately, the Z280 specifies the location of the interrupt jump table in any 16MB physical memory location, so I just need to ensure that it is unused and starts at the 4kB block boundary. The interrupt service routines must be in the logical 64kB space supported by the processor, and there is no such problem here.

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