Magic smoke and bouncy castles

[Richard Lewis]

So I've finally been able to build my MAX7000S 5V CPLD breakout board. In theory it should have worked but I couldn't initialize the JTAG chain so it failed. 

Thought I would share my observations in that it may be of benefit to beginners like me. 

After staring at the PCB layout I realized I made the following stupid mistakes:

1. It's a 4 layer board with an internal GND and PWR (5V) plane. No need to have copper pours connected to GND on the top and bottom signal layers. In fact it complicates the return path. A 2 layer board would have been easier but space constraints made routing power traces impossible. 
2. A 50mhz clock made me realize how lazy I have been with regard to PCB design in a <10mhz domain. At 50mhz effects of thin traces, length and how they are placed start to become an issue. I didn't take into account parasitic inductance, capacitance etc. Datasheets for some of the specialized components I used (like an ideal diode) have recommended layouts for traces. It's best to follow this. 
3. The bypass capacitors for the CPLD are on the opposite side of the board and do not directly connect to the VCC and GND pins on the CPLD. Instead there is a VCC via between the cap and the pin that creates a path through layer 3 which is connected to the VCC net. The result is significant switching noise being injected onto the power net in the form of ground bounce and voltage droop. I'll send an image later from my scope but it shows a significant ringing oscillation which is clearly ground bounce. Also, it was also stupid of me to route signal traces directly underneath the oscillator can. 
4. Not carefully checking the footprints for components. The KiCad library symbol I used for the voltage regulator had the pins assigned incorrectly. End result was that VCC and GND were swapped. Hence the blue smoke. 
5. On one side of the CPLD, the VCC and GND pins are adjacent. I should have routed the power traces in opposite directions. Instead the were routed in such a way that there was a major solder bridge that took a dental pick to remove 
6. For the copper pours I didn't use thermal reliefs for the TH parts. Soldering the pins connected to GND became a nightmare since the whole board acted a heatsink. Removing solder was not easy. 
7. The board is 900 mils wide so it will fit on a standard breadboard with 1 column on either side to spare. Not ideal but best I could do. However I had too much margin between the edge cuts and pins. I ended up having to sand the sides down so I could have room to fit the dupont wires. 
8. Turns out that using half-pitch 50mils (1.27mm) header pins for jumpers was a bad idea. Had to use tweezers and high magnification to place the jumpers. Also separating them from the header strip was frustrating. New design will use a 4 position DIP switch. 
9. This is the most important bit. I didn't prototype the schematic. If I had breadboarded the GPIO section I would have realized it had a major flaw. In the last image I intended for the LED to be controlled by 2 CPLD pins. Obviously the pins should be on the buffer input and LEDs on output. The result was that due to a soldering error I was directly pushing 150mA (the current limit set on the power supply) directly into a pin that can only sink 25mA max. So those 2 pins are toast... literally... 

[Greg Holdren]

See below. It kept renumbering the quoted text.

Greg

On Thursday, August 29, 2019 at 10:49:56 AM UTC-7, Richard Lewis wrote:

So I've finally been able to build my MAX7000S 5V CPLD breakout board. In theory it should have worked but I couldn't initialize the JTAG chain so it failed. 

Thought I would share my observations in that it may be of benefit to beginners like me. 

After staring at the PCB layout I realized I made the following stupid mistakes:

1. It's a 4 layer board with an internal GND and PWR (5V) plane. No need to have copper pours connected to GND on the top and bottom signal layers. In fact it complicates the return path. A 2 layer board would have been easier but space constraints made routing power traces impossible. 
2. A 50mhz clock made me realize how lazy I have been with regard to PCB design in a <10mhz domain. At 50mhz effects of thin traces, length and how they are placed start to become an issue. I didn't take into account parasitic inductance, capacitance etc. Datasheets for some of the specialized components I used (like an ideal diode) have recommended layouts for traces. It's best to follow this. 

What does the clock look like? Clock layout is priority. The trace lengths that your going are pretty short.

 

1. The bypass capacitors for the CPLD are on the opposite side of the board and do not directly connect to the VCC and GND pins on the CPLD. Instead there is a VCC via between the cap and the pin that creates a path through layer 3 which is connected to the VCC net. The result is significant switching noise being injected onto the power net in the form of ground bounce and voltage droop. I'll send an image later from my scope but it shows a significant ringing oscillation which is clearly ground bounce. Also, it was also stupid of me to route signal traces directly underneath the oscillator can. 

Yep avoid routing around the clock and clock line. It is ideal to put the caps on the top and have a 10mil or bigger trace connect to them. But what you did physically with the caps on the bottom is ok. It is very common. I guess part of the problem is no blind vias like you mentioned before or the via going to the power/gnd plane. You can double via the caps if there is room. Related to noise, how is the supply noise going in? Power by a battery and linear reg and look at the noise. Don't use the ground pigtail clip. There should be a small coiled spring clip that came with the probes if you have them. It is also better to use AC input mode for the channel if you have that option on your scope to measure pk-pk PS noise. It will look worse with the pig-tail.

1. Not carefully checking the footprints for components. The KiCad library symbol I used for the voltage regulator had the pins assigned incorrectly. End result was that VCC and GND were swapped. Hence the blue smoke. 

Based on experience I check everything along the way. Triple check everything and no assuming. :) Peer review is extremely important. 

1. On one side of the CPLD, the VCC and GND pins are adjacent. I should have routed the power traces in opposite directions. Instead the were routed in such a way that there was a major solder bridge that took a dental pick to remove

1. For the copper pours I didn't use thermal reliefs for the TH parts. Soldering the pins connected to GND became a nightmare since the whole board acted a heatsink. Removing solder was not easy. 

Yep, important. :)

1. The board is 900 mils wide so it will fit on a standard breadboard with 1 column on either side to spare. Not ideal but best I could do. However I had too much margin between the edge cuts and pins. I ended up having to sand the sides down so I could have room to fit the dupont wires. 
2. Turns out that using half-pitch 50mils (1.27mm) header pins for jumpers was a bad idea. Had to use tweezers and high magnification to place the jumpers. Also separating them from the header strip was frustrating. New design will use a 4 position DIP switch. 
3. This is the most important bit. I didn't prototype the schematic. If I had breadboarded the GPIO section I would have realized it had a major flaw. In the last image I intended for the LED to be controlled by 2 CPLD pins. Obviously the pins should be on the buffer input and LEDs on output. The result was that due to a soldering error I was directly pushing 150mA (the current limit set on the power supply) directly into a pin that can only sink 25mA max. So those 2 pins are toast... literally... 

Reviews and double checking as mention above. I don't think prototyping is necessary unless you don't know a particular part of the circuit will behave. This error should have been seen by schematic inspection. Was this the board that was sent out prior to posting the schematic? I don't remember this unless I glossed over it too. :)

The board looks good. Maybe work on the power distribution. This should work fine on round two. Post the design as you go and people can review.

[Bill Shen]

You are comfortable enough with SMT that you should be able to breadboard SMT with a single-sided copper clad board like the attached picture.  The IC is a MAX2 in 0.5mm lead pitch.  The important thing are hooking up power, ground and JTAG programming header.  The hookup wire is 30ga wire-wrap wire. 

A few tips:
* Bent the ground pins toward the copper foil and solder; cut the copper foil to create a thermal barrier (crude thermal relief) so you can solder ground to the copper foil.
* Bent the VCC pins upward to make them easy to solder.  Bring all VCC pins together in a ring (or grids in this case)
* Bent the JTAG pins to isolate them from other pins so soldering is easier.  You can also tombstone a high value SMT resistor near each pin to serve as anchor to guide the actual connection from the 30ga wire to the designated pin.
* For ease of soldering, you can solder a 30ga wire to two CPLD pins and program both pins the same functions.
* CPLD are remarkable resistant to mis-wiring.  It takes a lot to destroy a device.  Your device is most likely still functioning.
Have fun!
  Bill

[Phillip Stevens]

Richard Lewis wrote:

So I've finally been able to build my MAX7000S 5V CPLD breakout board. In theory it should have worked but I couldn't initialize the JTAG chain so it failed. 

Thought I would share my observations in that it may be of benefit to beginners like me. 

After staring at the PCB layout I realized I made the following stupid mistakes:

1. It's a 4 layer board with an internal GND and PWR (5V) plane. No need to have copper pours connected to GND on the top and bottom signal layers. In fact it complicates the return path.

I'm not sure that it is accurate to say leave "islands" of copper flood fill un-grounded. I can't quote a reference, but somewhere along my reading path I learned that this could be the cause of substantial EMI issues, as the islands of copper can resonate and become RF transmitters.

Whether this is important at your clock of 50MHz is not clear to me. On one side a harmonic resonance at 100MHz would be right in the middle of the FM Radio band, and would be pretty annoying. But, on the other side the wavelength of 50MHz is so long that it would be difficult to get effective coupling to any island resonators.

Interested to hear more on this.

Anyway, based on this idea, I tend to go around after I've finished a route layout and add GND vias to capture all fill islands. That way the vias are ensured of not being in the way of useful signals, and there is then an EMI insurance policy.

Cheers, Phillip

[Richard Lewis]

Hi Bill,

Want to give it a try but I might end up injuring myself :-). For SMD stuff I've been soldering the parts onto a small breakout boards and bread boarding it. It's OK as long as I keep the wires short and frequencies low. 

-Richard

[Richard Lewis]

Thanks Greg! 

I've taken your advice and reworked the layout and traces. Attached are the gerbers and schematic

It's a 4 layer board with this stack up: signal/GND/5V/signal

Since I have a dedicated ground plane layer not sure if I need to flood fill the signal layers with a GND plane?

Also, in case you are wondering, the reason why I'm using a lot of ideal diodes is because I have a lot (I accidentally ordered 20 instead of 2). Wanted to have reverse current protection and they have extremely low dropout compared to a Schottky.  

-Richard

[Greg Holdren]

Richard,

I took a look at the design files. Looks really good now. The cap placement is optimal and the thermal relief on the TH looks good. Clk is good and short. If you were to run the 50MHz clk some distance from the destination then keep the resistor near the osc. Nothing is near the trace.

Just a few minor things on the schematic and PCB:

1) On nets R3, 5, 7, I don't think pull ups are needed between the 244 outputs and the LEDs. Res R15 can be removed and use the res pack. Maybe other pull ups can be replaced too. I'm not sure of the value of the resistor pack.

2) Clk2 doesn't have a pull up or down. (unless the 7000 has programmable internal pullups)

3) Not a big deal since the trace/spacing is 1:1 and the runs are short but some of the traces can be spread out some. My OCD and I fight with the PCB layout people at work about this. :)

Double check schematic symbols with land patterns. The regulator looks like it was fixed.

There is no room for gnd fill on top. Board is small and tight. Rules would probably prevent much fill if any at all.

Ground fill is good for many reasons. Some not really a concern for your board.

1) Cross talk/Guard traces

2) EMI/RFI reduction. Smaller loop paths (current loops between gnd and source) reduces EMI emissions at given frequencies not at DC.

Adding GND fill on top/bottom helps with these points.

Here is an explanation from Howard Johnson, a signal integrity expert. Better than I can explain. The comment section has good reasons too.

https://www.edn.com/electronics-blogs/signal-integrity/4325321/Ground-fill

The author of the article came to HP where I was working at the time and taught a week long course about all this stuff.

Here is an EIO centronics printer interface card I did at HP in 2004. GND fill on the top as you can see and and on the bottom (more even), I'm pretty sure this is a 4 layer board. So the stack up on yours is similar to your board but with fill. Last year was the last time I saw the board offered on the HP site so it shipped for 13 years. Nice to see it on Rev A still. :)

https://www.amazon.com/HP-J7972G-Parallel-Interface-Card/dp/B000BS3IBY

Greg

[Richard Lewis]

Thanks again for the advice. I appreciate that I can have a professional engineer proofread my work!

1. I believe my thinking here was that when the CPLD initializes that the unassigned pins are by default pulled to ground. They can also be configured for weak pull-up but assumes the EEPROM FLASH has an image installed. Then on a blank CPLD I am assuming the LED's would be "on" when the board powers up. However, that's not necessarily a bad thing because it could be used as an indicator that the CPLD is not initialized. But yes, looking at it again I can see where pull-ups here probably won't work as intended. The resistor pack is 10K which I have since updated on the schematic. 

2. I think the data sheet mentioned I could leave the input only pins floating but recommended pull-ups anyway. Thanks, I'll add one anyway since it can't hurt. 

3. I know what you mean about OCD. I spend maybe 30 minutes doing the initial routing followed by days of "tweaking". However with a hyperactive 9 year old at home I have about 1 hr a day for tweaking. Also, somehow I've been conditioned into thinking that 90deg trace angles are wrong so I spend a lot of time "correcting." However Bill has conclusively proven (as well as David Jones on eevblog) that 90deg angles don't make much of a difference. I still prefer 45deg angles because of aesthetics. 

4. With regard to GND fill, I've been reading that with a 4-layer board and a dedicated GND layer top and bottom fills shouldn't be needed especially if the board density is high. Otherwise if the fills are mostly islands and not properly stitched they can act as patch antennas. I'm certainly not looking for FCC certification with this board. Also, none of the cheap fab houses support micro-vias so it's hard to find space on the boards for stitching with "regular" sized vias. As an aside, it does remind me of my TRS-80 Model 1. I would turn it on in my upstairs bedroom and my parents couldn't watch TV on the opposite corner of the house because of the EMI. I think that is why Radio Shack had to create the Model III because the Model 1 couldn't be properly shielded. 

5. I ran into some of Howard Johnson's work. Makes me think of pancakes for some reason...

-Richard

[Greg Holdren]

Sure thing....

1) There should be a place to select the behavior on a project to project basis for unused IO. A personal preference to make them Hi-Z.

2) Internal pull-ups can be somewhat weak since they can be in the high double digit K ohms. Noise on the pin trace could trigger the threshold due to higher impedance. YMMV

3) For the frequencies/edges we are working with 90 or 45 degrees is fine. I prefer 45 since it looks better plus it helps the lazy electrons change direction easier. :) High speed DDRx and Diff signal is a must for 45/rounded traces for direction changes and length matching.

5) Yeah... think the same thing.:) I don't think we have any around us anymore in Cali.

Greg

[Tom Storey]

On Thursday, August 29, 2019 at 6:49:56 PM UTC+1, Richard Lewis wrote:

This is the most important bit. I didn't prototype the schematic. If I had breadboarded the GPIO section I would have realized it had a major flaw. In the last image I intended for the LED to be controlled by 2 CPLD pins. Obviously the pins should be on the buffer input and LEDs on output. The result was that due to a soldering error I was directly pushing 150mA (the current limit set on the power supply) directly into a pin that can only sink 25mA max. So those 2 pins are toast... literally... 

Why such low value resistors for your LEDs?

I find with modern LEDs (and I guess depending on the colour) I can use even a 3.3K at 5V and still get quite an acceptable level of brightness - if simple indicating is the aim of your game, and not an aircraft search light. :-)