RomWBW for John Winans' Z80Retro

[Bill Shen]

Wayne,
Z80retro is a Z80 designed by John Winans and there are several dozen well-done YouTube videos (John's Basement channel) explained the design in details, so there are general interests in this Z80 design which has a 10MHz Z80 with 512K RAM, 128K flash and SD card, and design information are available on GitHub.  I know RomWBW support a "Z80Retro", but that's Peter Wilson's design which is not the same as John Winans'.

I'm trying to port RomWBW to John Winans' Z80retro, but I ran into a problem:  the bank register and SD bit-bang controls are on the same IO register.  The register is write-only, so the current bank value need to be stored in HBIOS memory somewhere.  Everytime I write to bank register, I need to append the inactive state values of the SD bitbang controls and everytime I bit-bang the SD, I need to make sure the current bank register value is append to SD bitbang controls.  This actually all worked and I'm able to reach RomWBW's sign-on screen.  RomWBW is able to initialize the SD card and reported the correct type and size of the card.  So that's all good...  

Now, the problem I'm having is CP/M.  When I load CP/M with 'c' command, it hangs.  I think the reason is because the current bank reg value is not passed to CBIOS, so when CP/M manipulate the bit-bang SD, it didn't append the current bank value and the program crashed.  My question is how does RomWBW handles situation where bank register and SD bit-bang controls are on the same register and how that information is passed to CBIOS so its SD read/write routine can also deal with this combined bank_reg+SD_bit_bang register?  Below is the RomWBW signon message:
-------------------------------------------------------------------------------
Boot [H=Help]: r

Restarting System...

RomWBW HBIOS v3.5.0-dev.20, 2024-09-09

Z80Retro [Z80RETRO_std] Z80 @ 7.372MHz
0 MEM W/S, 1 I/O W/S, INT MODE 2, ZRC MMU
0KB ROM, 512KB RAM, HEAP=0x54D7

CTC: IO=0x40 NOT PRESENT
SIO0: IO=0x32 SIO MODE=38400,8,N,1
SIO1: IO=0x33 SIO MODE=38400,8,N,1
MD: UNITS=2 ROMDISK=0KB RAMDISK=256KB
SD: MODE=Z80R IO=0x10 DEVICES=1
SD0: SDHC NAME=TEAM BLOCKS=0x00EE2000 SIZE=7620MB

Unit        Device      Type              Capacity/Mode
----------  ----------  ----------------  --------------------
Char 0      SIO0:       RS-232            38400,8,N,1
Char 1      SIO1:       RS-232            38400,8,N,1
Disk 0      MD0:        RAM Disk          256KB,LBA
Disk 1      MD1:        ROM Disk          0KB,LBA
Disk 2      SD0:        SD Card           7620MB,LBA


Z80Retro [Z80RETRO_std] Boot Loader

Boot [H=Help]: c

Loading CP/M 2.2...

CBIOS v3.5.0-dev.20 [WBW]

It hangs here.

[Wayne Warthen]

CBIOS does all I/O via HBIOS, so that should not be an issue.

I notice the ROM Disk is enabled, but is size 0KB.  That probably won’t work.  Set MDROM to FALSE.

Thanks. Wayne

[Bill Shen]

Wayne,

Thanks for the explanation that CBIOS is linked to HBIOS.  I’ve been hacking at HBIOS and SD.ASM to make it work for Z80retro, so I’ll check my hacking to see where I broke the CBIOS.  First, I’ll set MDROM to FALSE and try again.

  Bill

[Alan Cox]

It's worse than it sounds. That particular Z80Retro (there are two confusingly - the long standing one which is already supported and the "2063" one by John) also has the problem that because the SD and banking share the register not only do you have to worry about bank numbers when doing SD but you also have to worry about the correct state of all the SD bits when handling an interrupt bank switch.

For Fuzix the only way I could make it work was to just accept SD transfers running with interrupts off and crap IRQ latency.

Alan

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[Wayne Warthen]

Hi Bill,

I quickly reviewed the architecture of the Winan Z80-Retro.  The other thing that you might be having an issue with is that the 'C' option of the boot loader is going to try to load CP/M from ROM.  However, I don't think there is any reasonable way to do that since the ROM is not banked.  It looks like it just overlays the entire Z80 address space when enabled.  Alternatively, you could try booting CP/M from the SD card.

Thanks, Wayne

[Bill Shen]

Wayne,
I'm running Z80retro as 0K ROM, 512K RAM where RAM is loaded with RomWBW software either via serial port or from SD card.  

Set MDROM to FALSE help some, but I'm experiencing strangeness that are not consistent so I think Alan's explanation may be correct that I'll need to turn off interrupt while executing SD_PUT or SD_GET routines.
  Bill

[Wayne Warthen]

You could just set INTMODE to 0 in RomWBW config (at least for now).

-Wayne

[john winans]

Yes.... you REALLY DO NOT want IRQs on during the SD bit-banging!
Sharing these bits in the same register was a space-saving choice.
If you want to improve your IRQ latency, you can EI and then DI in the the data transfer loop between every N bytes as long as you have the right value in the IO cache byte.  Make sense?

Also note that someone has a pull request in there with SD bit-banging optimizations that I have yet to verify.  (Too much work, weddings, birthdays,.... my life used to be so much simpler in the '80s.)  I mention it in case there are any gems in there that you might want to know about.

[Bill Shen]

I'm still not making progress with porting RomWBW to Z80retro (2063).  It can boot RomWBW and detects SD card, but then crash when run CP/M2.2.  Anyway, that's not the reason for this post.

I have designed a Z80retro-to-RC2014 backplane.  At the edge of Z80retro board is a 2x20 footprint with all Z80 signals, in fact, they are the same pin assignments as the Z80.  So it makes sense to have a Z80-to-RC2014 backplane connecting to the 2x20 header.  I debated with myself about a side-by-side backplane or a stacked-up backplane on top of Z80retro.  It occured to me that because the classic RC2014 is single row of 40-pin connector, boards can be plugged in either on top or from the bottom.  Another word, the same Z80retro-to-RC2014 backplane can be connected side-by-side or flipped over and stacked on top of Z80retro.  However, it requires two different built of Z80retro and backplane: 1), 2x20 right angle male header on Z80retro that plugs into 2x20 right angle female on the backplane; or 2), 2x20 straight long male header that plugs into 2x20 female mounted on bottom of the backplane.   Here are two pictures of side-by-side and stacked configurations.  More importantly, they work in both configurations.
Bill

[Bill Shen]

I *THINK* have successfully ported RomWBW to Z80retro, but I don't really understand why it worked.  

The biggest porting obstacle with Z80retro is the bank register shares the same latch as the bit-bang SD register, and the latch is write only.  My original solution is saving the value of the latch in memory so when manipulating bank register, the current value of bit-bang SD is not changed; similarly, when manipulating the bit-bang SD, the current value of bank register is not changed.  This method didn't work and I think it is because the memory that stored the bank+SD values is swapped out as RomWBW alternating between SD routine and banking routine.  In the course of trying other methods, I inadvertently disconnected the shared memory between SD routine and banking routine; suddenly everything is working!

Retracing my "mistake", I believe bit-bang SD and banking are mutually exclusive, even with interrupt enabled.  It appears that bit-bang SD is always done in bank 0, so I don't need to save and append bank value; and banking happens only when SD is inactive, so I don't need to save and append transient SD states, just force SD to inactive state when banking.

So I ported RomWBW to Z80retro without sharing bank+SD register between the SD routine and banking routine and it seems to work just fine even with mode 2 interrupt enabled, but I'm worrying there is a bug lurking somewhere.  Is there a test I can do to flush out the bug?
Bill

[Wayne Warthen]

Wow, congrats Bill.

Indeed, you may have gotten lucky to some extent.  Yes, the SD access would normally occur only from within the HBIOS bank (the first RAM bank).  So, if the SD routines keep the bank select bits appropriate for RAM bank 0, then it could be OK.

It does seem like there is still the potential for an interrupt to muck up an in-progress SD access.  When an interrupt fires, RomWBW will write to the bank select port to select the HBIOS bank (even if it is already selected).  Depending on where in the SD Card processing an interrupt occurs, I would expect it to break.  To try and cause this break to occur, you would want to try and generate as many interrupts as possible during a CF Card I/O.  I'm not sure what kind of interrupts the Z80Retro generates.

Thanks, Wayne