Wait state generator for 20MHz Z80

[Mark T]

I was going to try and build a wait state generator to add one wait state to each memory access in order to investigate the max speed I can get my Z80 single board CP/M running. This was after receiving another set of supposed 20MHz Z80 from Polida only to find the maximum speed I can run is still 12MHz. It seems to run at 20MHz clock while in bootstrap mode, where instructions are fetched from the FT245, but crashes when it tries to run the bootstrap payload. If I can add a wait state I might be able to verify if the processor runs on a 20MHz clock and confirm if its the memory access speed causing the problem.

Problem is that all the examples of a wait state generator that I've found are from documents when 4MHz Z80 was the fastest available. Example below is from the 1982 Mostek designers guide.

If I look at the timing spec for Z84C0020, the max time from Clock fall to MREQ fall is 40ns, while clock pulse width low is 25ns at 20MHz, which means the example wait state generator would activate WAIT for the falling edge of T3 instead of T2.

Does anyone know of any examples of a wait state generator for a 20MHz Z80?

I think the following might work, but would be nice to see some known working examples if possible. Its also annoying that TTL seems to be missing open collector OR gates

Mark

[Tom Szolyga]

Perhaps faster logic is required.  Consider that the max prop delay for a 74LS74 is 40ns from clock to Q output.  A 20MHz clock has a 50ns period or a 25ns high and 25ns low period.  It seems the flip flop might not change state before the next clock edge arrives.  ALS or AS is a faster family.

Tom

[Richard Lewis]

As Tom mentioned either faster logic, the prop delay from a 74AHCT74 for example is around 5-10 ns or a small CPLD like a MAX7000 would be easy to implement in Verilog/VHDL. 

[Mark T]

Thanks guys

I think its going to take a bit more than just faster logic. MREQ low from T1 clock falling edge is 40ns max and WAIT setup time to T2 clock falling edge is 7.5ns max. Worst case this gives me 2.5ns from MREQ low to assert WAIT low.

Maybe I can get something to work if I treat /WAIT as DTACK, keeping /WAIT active until MREQ or IORQ is low. This would add a wait state to IORQ, but this would be masked by the automatic wait state already included for IO operations..

Using 74ALS74 in the following circuit might work. Relies on MREQ low from T1 clock falling edge (<40ns) + 74ALS74 D setup (<6ns) to be greater than CLK low (25ns).

Mark