CPM-ready Z80 SBC jumps the shark!

[Bill Shen]

I have designed several CPM-ready Z80 SBC in the last couple years.  The design is getting simpler and simpler and I'm wondering what an over-the-top, simplest, publicity-seeking stunt of most irrevant CPM-ready-Z80-SBC might look like.  Z80 is given, it needs RAM, and I'm CPLD kinda guy so it will be Z80+RAM+CPLD for simplicity; it won't have PC board, all handwired for over-the-top effect; it is arranged in 3-D stack for publicity stunt.  I christen it the Z80+RAM+CPLD Single-Blob-Computer or ZoRC .

Now I have a stolen name and a quixotic quest, how do I really do it with just Z80, RAM, and CPLD and handwire it all?  Well, I haven't done it so the jury is still out, but here is the plan (and like all plan, it'll change); To minimize manual wiring, a 32-pin DIP 512Kx8 RAM is turned upside down and wired directly to a 40-pin DIP Z80.  The signals do not match exactly, but 18 pins do match so that save a good number of manual wiring.  The CPLD will drap over the RAM and signals assigned such that they map closely to the signals below.  No doubt the CPLD will change numerous times so a programming header will be tacked in but eventually removed.  22MHz oscillator sits on top of the CPLD.  It will be powered by an USB-to-serial adapter.  It will have connector to drive an array of WS2812B RGB LEDs, and possibly a 128x64 OLED display.  I actually has a sketch of this idea.

Software-wise, the CPLD has a simple boot ROM, serial port, memory bank controller, and glue logic.  The boot ROM checks the serial port for input, after a while jump into memory if no serial input is detected; or if serial input is detected, loads 256 bytes of bootstrap code and jump into the bootstrap.  The 512K RAM has 16 banks of 32K.  Top 32K is common memory; bottom 32K is for power-on monitor.  CPM takes another 32K, the remaining is RAMdisk.  Oh, I know I'll need a nonvolatile memory controller and a super capacitor, but I'll cross that bridge if and when I ever got close to it.

Let the quest begin...

  Bill

[Colin MacArthur]

Looks like a FUN project, can't wait to see a PIC...

CM

[Mark T]

Hi Bill,

I can put a copy of my hacked version of RomWBW onto github as a starting point if you are interested. It builds a 512k image to run on ram only, with 384k ram disk, preloaded with a subset of programs but not write protected like the standard Rom disk of RomWBW. Powershell is updated to automate the build of the image.

The bootstrap loader included is for my single board cpm module, using ft245 to provide instructions to the z80 until bootstrap mode is disabled. I was thinking a cpld could provide instructions from serial interface in a similar way.

Mark

[Bill Shen]

Mark T,
I love to have your version of RAM-only ROMWBW.  I do have several Z80/Z280 designs with 512K RAM that I like to port ROMWBW to.  Even with 128K of RAM in 4 banks and a CF drive, it should be able to substitue the RAM & ROM drives with CF drive and work the banks with 128K of RAM. 
  Bill

[Mark T]

Hi Bill,

Just uploaded at :-

https://github.com/markt4311/RomWBW-512K-RAMONLY

This is from an old version of RomWBW, but I've only uploaded the hbios and buildrom.cmd, so it may not assemble without errors if you use with a newer version of RomWBW.

It should be possible to find all changes in hbios by searching for PLT_MT.

sd.asm also contains the changes for the shift register spi uSD card interface.

Mark

[OscarV]

Bill,

Think of FeRAM or MRAM for memory. Eliminates your nonvolatile memory controller and truly keeps it to 3 ICs! (and AFAIK nobody in the retro community ever tried these new nonvolatile RAMs...)

Kind regards,

Oscar.

[Bill Shen]

Thanks for the suggestion.  Both FeRAM and MRAM are interesting.  I've worked with them during their early days.  I looked into them just now, FeRAM seems to be mostly in form of serial EEPROM, and MRAM are only available with 3.3V supply, so unfortunately they may not work with the 5V Z80.
  Bill

[Bill Shen]

Here is the schematic of ZoRC.  Might as well get on with it and see what obstacles I'll run into.
  Bill

[Bill Shen]

This is where I am tonight with ZoRC:  It is certainly a tangled mess, not quite what I've imagined.  ZoRC is on a single-sided copper board for mechanical support.  The bottom is Z80, middle is RAM, CPLD is on top of RAM and oscillator on top of CPLD.  CPLD is programmed via the 2x5 header.

I can see Z80 booting from CPLD, but something is wrong with the serial port so Z80 can't load program from serial port into RAM.  I need my beauty sleep, I'm calling it a night.
  Bill

[Xander Soldaat]

Hi Bill,

I see quite a few boards out there with CPLDs. What exactly are they used for? Is it basically to replace all of those discrete logic chips that are used for the address selecting of devices on the bus (I forget what the actual term is)? 

= Xander

[Bill Shen]

Xander,

CPLD or Complex Programmable Logic Device and its predecessor, Simple Programmable Logic Device, were designed mainly to replace TTL logic.  They reduce hardware cost, parts inventory, and pc board size.  CPLD/SPLD consisted of programmable combinatorial logic and some flip flops.  They were popular from the 2nd half of 1980's until end of 1990's; they are mostly replaced by FPGA now.

I used CPLD extensively because it is a 5V part unlike the current FPGA which are 3.3V or lower.  IMHO, Altera had over-designed its EPM7000 family and its many capabilities were not fully explored during its brief life.  The many CPLD designs represent my exploration of the capability of CPLD that I didn't know about in the 1990's.  
  Bill

[Bill Shen]

Ha, it is alive!  The design is close enough to ZRCC that the existing ZRCC serial loader and monitor work as is.  Even SCMonitor with Startrek is working.  I guess it is time to do 'testing' with complex software like Startrek...  :)
  Bill