While waiting for pc boards to arrive from China, I've been puttered around with a commercial Z84C15 with KIO daughterboard that was a part of Maxtrix Platemate motherboard. The pc boards from China will be here in a couple days, so I'm documenting the tearing down & modification of the daughter board (designated as OPALJENA) before I get sidetracked.
OPALJENA is a 3.3" X 4" 4-layer pc board consists of a Z84C1510, Z84C9010 (KIO), 32x8 RAM, and a ROM. The oscillator is 19.66MHz which is divided by two to run the CPU at 9.83MHz. There are a couple glue logic, 74HCT139, 74F32 and a programmable logic. The ROM is socketed so it is easy to replace it with my own software.
The first step is to find suitable VCC and ground, power it up and see what happen. OK, no blue smoke, drawing a nominal current of 80mA. There are activities on address lines, so that's all good.
Next step is locating the transmit and receive signals of Z84C15 and connect a USB-serial adapter to it, replacing the ROM with W27C512 with my own simple diagnostic and see if it will talk. Attached picture shows the points of interests for the first couple steps.
The serial port does work, but it is running at 38.4K baud. So while the processor clock is 9.83MHz, the I/O clock is 1/16 of that. This is because the clock is divided by 16 with 74HCT139 and feed to both KIO and serial ports of Z84C15.
So far everything were done without modifications, other than replacing the ROM. Further poking around show Z84C15's CS0 is wired to ROM gated by 74F32 with nMREQ; Z84C15's CS1 is wired to RAM also gated by 74F32 with nMREQ. This is a problem because I won't be able to page out the ROM completely even though the memory map of CS0 and CS1 are programmable. The critical area from 0x0-0x100 will always be ROM space.
So to make it capable of running CP/M, I need to make significant modification to the pc board.
To be continued...