We are looking for Physical Design Engineer in Mountain View, CA - Onsite

[Aswin]

Only USC, H4 EAD, L2S

 

 

We are looking for Physical Design Engineer in Mountain View, CA - Onsite

 

What You will Do:

 

·         Drive ASIC physical design implementation from floor planning through signoff.

·         Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization.

·         Achieve Power, Performance, and Area (PPA) targets.

·         Develop and validate timing constraints and perform Static Timing Analysis (STA).

·         Execute LEC, VCLP, and EMIR signoff activities.

·         Collaborate with cross-functional teams to resolve implementation and timing challenges.

 

Required Skills:

 

Strong experience in ASIC Physical Design.

 

Hands-on expertise in:

 

·         Floor planning

·         PnR

·         CTS

·         Timing Closure & STA

·         Timing Constraints

·         PPA Optimization

·         LEC

·         VCLP

·         EMIR

·         Ability to independently drive design closure and solve complex implementation issues.

 

Qualifications:

·         Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

·         Experience with advanced-node ASIC/SoC designs is preferred