Error with HLS auto genrated IP in the XPS design flow

[Umair Riaz]

Hello group,

I am using a recent develop branch of ReconOS and using sort demo as basis for my design. I changed the sort demo HLS code to use float instead of uint32. I ran RDK export_hw and HLS generation completed successfully with two Auto generated IPs for int to float conversion, also following information is given: (don't know if its relevant)
INFO: [SYN 201-210] Renamed object name 'rt_imp_fcmp_32ns_32ns_1_1' to 'rt_imp_fcmp_32ns_cud' due to the length limit 20

The generated RTL folder looks like :
rt_imp_ram.vhd
rt_imp_uitofp_32nbkb.vhd
rt_imp_fcmp_32ns_cud.vhd
rt_imp.vhd
rt_imp_ap_fcmp_0_no_dsp_32_ip.tcl     // tcl Script for  ip addition in Vivado
rt_imp_ap_uitofp_4_no_dsp_32_ip.tcl   // tcl Script for  ip addition in Vivado

But, RDK makes pcore  *.pao file as

lib reconos_v3_01_a reconos_pkg vhdl
lib rt_mydemo_v1_00_a    rt_mydemo vhdl
lib rt_mydemo_v1_00_a    rt_imp_ram vhdl
lib rt_mydemo_v1_00_a    rt_imp_ap_uitofp_4_no_dsp_32_ip vhdl    // But   NOT  a VHDL
lib rt_mydemo_v1_00_a    rt_imp_fcmp_32ns_cud vhdl
lib rt_mydemo_v1_00_a    rt_imp_ap_fcmp_0_no_dsp_32_ip vhdl    // But  NOT  a VHDL  
lib rt_mydemo_v1_00_a    rt_imp vhdl
lib rt_mydemo_v1_00_a    rt_imp_uitofp_32nbkb vhdl


So During running xps run bits i get error that the *dsp_32_ip.vhdl is not found. I removed the tcl file inclusion from *.pao file. And then ran the XPS again synthesis is fine but till NGDBuild: It detects the IP rt_imp_ap_uitofp_4_no_dsp_32_ip module down in the hierarchy

ERROR:NgdBuild:604 - logical block
   'slot_0/slot_0/rt_imp_inst/rt_imp_fcmp_32ns_cud_U2/rt_imp_ap_fcmp_0_no_dsp_32
   _u' with type 'rt_imp_ap_fcmp_0_no_dsp_32' could not be resolved. A pin name
   misspelling can cause this, a missing edif or ngc file, case mismatch between
   the block name and the edif or ngc file name, or the misspelling of a type

   name. Symbol 'rt_imp_ap_fcmp_0_no_dsp_32' is not supported in target 'zynq'.

Please inform how to add an IP module that HLS creates automatically into the XPS design flow.


Many thanks for reading long post.

Best Regards
Umair

[Christoph Rüthing]

Hi Umair,

exciting to see, that there are so many people working with ReconOS. So let me help you with your problem.

While I developed some more advanced hardware threads I also encountered this issue, since some of the components instantiated by the HLS synthesis are not generated as plain vhdl code but, as you already mentioned, generated by some tcl scripts. In the past, I was unable to port or integrate these scripts into the XPS design flow. Therefore, I took a slightly different approach and synthesized the entire hardware thread in Vivado and used the resulting netlists as black-box-defintions in the XPS design flow. That worked very well and is integrated seamlessly into the RDK.

Unfortunately, this feature is only available in the lates develop_ic branch. However, you should be fine to switch to that branch, since there are manly updates regarding a new interconnect for communication of hardware/software threads and improvements on the toolchain. If you use the develop_ic branch, you can simply specify "bbd" after you HwSource in your build.cfg. This causes the toolchain to issue the Vivado synthesis and integrate your hardware thread using the generated netlists, no further work needed. You can look into https://github.com/ReconOS/reconos/blob/develop_ic/demos/eval_pipe/build.cfg#L85 for an example how it might look like.

Hopefully that helps you with you problem. If you have any futher questions feel free to ask, you are always welcome.

Yours,

Christoph

Umair Riaz <umai...@gmail.com> hat am 13. Januar 2017 um 16:24 geschrieben:

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[Umair Riaz]

Hi Christoph,

Thank you for your support and help. As you suggested to use vivado and bbd, I already tried this with develop branch and Vivado synthesis was successful but not XPS(Missing bbd).
I will switch to develop_ic branch and try it now. Will discuss further about my progress.

Best regards,
Umair

[Umair Riaz]

Hi Christoph,

I tired eval_pipe demo and during HLS generation i get errors:
ERROR: [HLS 200-101] 'export_design': Option '-format' cannot have value 'pcore'.

Which HLS version is supported for this command? And what is version of working linux_xlnx and u-boot too?

Best regards
Umair

[Guanwen (Henry) Zhong]

Hello Umair,

For your problem, actually you can use Vivado HLS to generate a EDK pcore and see how it looks like. The problem you have is that EDK does not generate the corresponding netlist for you.

Once you generate a EDK pcore with Vivado HLS, you can see a folder under "HLS-solution/impl/pcores/rt_imp_top_v1_00_a/". (1). Inside the folder, you can copy the files in /data subfolder (you might need to change the filenames) to your custom IP folder to EDK. There is one file, "rt_imp_top_v2_1_0.tcl", which is used to generate the netlist files for you functional units. You can reuse it (need to change the "synhdl" at line 7 to "hdl").  (2). create a "your_pcore_path/hdl/vhdl" in your pcore folder, copy "*.xco" files in "HLS-solution/impl/pcores/rt_imp_top_v1_00_a/synhdl/verilog/" to "your_pcore_path/hdl/vhdl/"; (3) copy "*.vhd" from "HLS-solution/impl/vhdl/" to "your_pcore_path/hdl/vhdl/". (4) wrap "rt_imp.vhd" with your custom IP top files.

Then you should compile the whole project without errors.

Thanks,

Guanwen (Henry)

[Christoph Rüthing]

Hi,

sorry for the late reply, but I had no time the last days. The procedure you are describing, Guanwen, should be the one implemented in the ReconOS RDK in the develop_ic branch when using the bbd option. However, the error posted by Umair:

ERROR: [HLS 200-101] 'export_design': Option '-format' cannot have value 'pcore'.

is related to the newest HLS versions. Unfortunately, the export_design command supports the pcore format only up to version 2015.4, i.e. all later versions will fail. So which versions are you two using? Or have you another command for generating an EDK pcore in HLS, Guanwen?

Yours,
Christoph

--

[Guanwen (Henry) Zhong]

Hi Christoph,

I generate all source files manually instead of using the ReconOS RDK, so that I have more control on my project and later integrate my scripts. :-)

The version of Vivado HLS I use is 2014.4 and the command I use to generate pcores is "export_design -evaluate vhdl -format pcore -use_netlist ip". The new version HLS might provide scripts to generate the netlist, but I haven't update my tool, so I can not suggest how to deal with it.

I got your point, for new version Vivado HLS, as the EDK is no longer supported, they might remove this option. Thus Umair had this issue. In this case, he can follow your instructions to generate netlist with Vivado. Or he can install an old version ISE to generate the netlist (with the same source files created by new version Vivado HLS).

Thanks,

Guanwen

[Umair Riaz]

Hi all,

So I finally got the compilation working. Here are the details:
I have latest 2016.4 Vivado & HLS and worked on latest reconos develop branch with sort_demo modified  to use float. With following options, I ran RDK
HwSource = hls,bbd,vivado

RDK export_hw does HLS synthesis first and generates vivado ip scripts. I added them manually into script_vivado_edn.tcl in Reconos/templates/thread_hls_build. Vivado generates the edif files with nested edif. But the pcore generated by RDK does not include all files generated. So i have to manually add the generated edif files in pcore directory and modify the bbd file to include these edif files. After this the XPS system generation and bit stream generation is successful.

Kind regards
Umair

[Guanwen (Henry) Zhong]

Hi Umair,

The reason that rdk doesn't copy all generate edif files to pcore project is that in Line 158 and 160 (https://github.com/ReconOS/reconos/blob/develop/tools/_pypack/reconos/scripts/hw/export.py), rdk only writes "rt_imp.edn" to *.bbd file and copies "rt_imp.edn" to netlist folder.

If you want to do it automatically, you need to 1. use "shutil2.listfiles" to get all filenames with "edn" extension; 2. modify "srcs" in Line 158 to include the absolute paths of all netlist file (in order to copy those *.edn files to pcore folder) and 3. "incls" in Line 160 to include the names of all netlist file (eg. incls=[netlist_filenames], where netlist_filenames = "func1.edn,func2.edn,rt_imp.edn") 

Thanks,

Guanwen