Transmitter Modulation

[NZ0I]

I found a SPICE model for the J309 JFET (which should be similar to the obsolete part you have) and added it to my driver/modulator model. Getting it to work required some jiggering with component values, in particular R808 and R809. That is, I had to adjust the gain of U805 and the audio signal level coming out of U804. The model uses a 10k pot with a 20k resistor in series with the wiper for setting the JFET bias, and the pot's wiper is set to 20% above ground / 80% below +5V. The model assumes a 260mV peak VHF signal coming from the Si5351, and a 1.2V peak audio modulation. The (rather messy) model and the oscilloscope showing the audio modulation signal, and the modulated output are shown below.

Just eyeballing it, it appears that an adequate amount of modulation can be applied to the carrier by this circuit. But the model has some limitations, and we should expect that it will be necessary to experiment and tweak values to get it working. One limitation of the TINA analyzer, it seems, is that the oscilloscope can't keep up with the calculations necessary to display a modulated VHF waveform at slow scan speeds. It appears to get bogged down trying to fill in all the many thousands of sine wave points inside the envelope, and takes ridiculously long to display even a single envelope cycle. What is shown above in the oscilloscope display is actually a 100kHz signal being modulated by a 500 Hz audio signal. If I had used a 144MHz carrier then the simulation would run out of memory before displaying any useful information. Perhaps there is a setting in TINA that will let me work around that, but I haven't found it yet. But until we can see how the circuit is actually working at 144MHz (or simulating at that frequency), there will be some doubt as to how well it is going to work. But looking at the gain plot in TINA, it appears that it should work at 144MHz, with perhaps some component value tweaks.

[NZ0I]

I fleshed out the topology for the 2m transmitter and uploaded the schematic to the shared drive - Rev B.18. The DAC has been removed in favor of a PWM output from the processor, going into another LPF, to provide a variable voltage so the processor can adjust the transmitter gain.

The entire transmitter from oscillator to antenna output fits across the width of one schematic page, and I think there will be more opportunities to further simplify the design. But I'd prefer to start with more components and features than we necessarily need for the earlier designs, and then do cost cutting and simplification. Any extra/unneeded component footprints might come in handy for modifying the first boards if need be, and it is just more interesting to play with new features.

The first cut at the 2m Tx portion of the schematic is shown below. Please let me know if you have any suggestions, or notice any errors.

[NZ0I]

I've uncovered a few errors and better approaches to the design. The most serious error found thus far is the placement of R803. It should be placed between the output of the LPF that generates TX_GAIN, and the gate of the JFET. Otherwise, the AM_MODULATION would be driving the low-impedance output of the TX_GAIN op amp (unsuccessfully) and there would be no modulation. 

I've also added flexibility in the matching between the driver op amp (OPA355) and the final transistor (BLT50). I did that because the gain of the OPA355 at 146MHz will only be about 5dB in our circuit, and the voltage might not be sufficient to drive the BLT50. But the OPA355 can deliver plenty of power (higher current) if adequately matched, so I've added the components that NXP shows in their class B test circuit. We might discover that we can simplify things, but better to have the flexibility in the initial design.

I also rearranged a few components in the VHF output filter and adjusted the trimmer ranges. Modeling suggests that this filter should do a better job of bringing down the 2nd harmonic than the filter used in Jerry's 2m design, but at the cost of several more components. I will do some more modeling to see if a lower-order filter might get the job done... but what is shown in the figure below should be effective.

I've placed schematic Rev B.19 on the shared drive. But the Tx design is still new, and not fully modeled (much less built and tested), so expect changes... but hopefully nothing too radical in the 2m Tx chain.

On Wednesday, February 15, 2017 at 9:16:40 AM UTC-5, NZ0I wrote:

[NZ0I]

Also, I noticed this encouraging statement in the BLT50 spec:

Ruggedness in class-B operation

The BLT50 is capable of withstanding a load mismatch corresponding to VSWR = 50:1 through all phases at rated output power, up to a supply voltage of 9 V, f = 470 MHz and Ts ≤ 60 °C, where Ts is the temperature at the soldering point of the collector tab.

I suppose its ruggedness might be somewhat reduced at 146 MHz versus 470 MHz, since the device might be delivering higher power at the lower frequency. But still, this seems like a pretty rugged part. Giving the processor the ability to monitor SWR (or just transistor temperature using an LM20) and throttle the TX output power might be all that is required in order to protect the part in the event that the antenna gets removed while the transmitter is on the air. 

On Wednesday, February 15, 2017 at 9:16:40 AM UTC-5, NZ0I wrote: