Williams System 6 eprom/ram chip address

[infrared pinball]

Hello,

i see in Williams system 6 MPU schematics that every eprom/ram/pia on the board has one address. for example IC17 has 7800. How this address computed.

Can anybody explain the theory about this ?

Best regards
Michael

[John Robertson]

The address given is the Start address for the memory location of the
device. The ROM in this case uses memory space 7800h to 7FFFh with the
'h' for Hexadecimal notation. This aids folks using tools such as the
Fluke 9000 series of microprocessor analysis machines to do a memory
check or an I/O check.

To get into the background of memory maps and allocation of memory space
is beyond what I want to type today.

Read up on the microprocessor device used, either 6800 or 6802, and
learn how microprocessors interact with RAM, ROM, and I/O, there are
mamircony online courses. The normal memory space used by 8-bit
processors is 64k, but the early games used just 32k and mirrored the
memory table by ignoring Address 15 to save on chip count.

Have I lost you yet?

John :-#)#

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[Kerry Imming]

On 11/14/2022 9:29 AM, John Robertson wrote:
> On 2022/11/14 4:46 a.m., infrared pinball wrote:
>> Hello,
>>
>> i see in Williams system 6 MPU schematics that every eprom/ram/pia on
>> the board has one address. for example IC17 has 7800. How this address
>> computed.
>>
>> Can anybody explain the theory about this ?
>>
>> Best regards
>> Michael
>>
>
> The address given is the Start address for the memory location of the
> device. The ROM in this case uses memory space 7800h to 7FFFh with the
> 'h' for Hexadecimal notation. This aids folks using tools such as the
> Fluke 9000 series of microprocessor analysis machines to do a memory
> check or an I/O check.
>
> To get into the background of memory maps and allocation of memory space
> is beyond what I want to type today.
>
> Read up on the microprocessor device used, either 6800 or 6802, and
> learn how microprocessors interact with RAM, ROM, and I/O, there are
> mamircony online courses. The normal memory space used by 8-bit
> processors is 64k, but the early games used just 32k and mirrored the
> memory table by ignoring Address 15 to save on chip count.
>
> Have I lost you yet?
>
> John :-#)#
>

Adding a little... On my Gorgar schematics, different devices show
different addresses. IC17 = 7800, IC20 = 7000, IC26 = 6400, etc. Are
you using the original schematics for your game?

Decoding of address bits A12:A9 is done by IC15, a 74LS139 decoder.
IC15 decodes those upper address bits into chip selects for the RAMS/ROMS.

- Kerry

[infrared pinball]

Thanks all for your answers,

the schematics of my pinball i was looking is Firepower.

I just wonder why for example IC14 (2716) has address 6000 hex (01100000 00000000 binary) and not something else.
If someone else creates a simple board with a processor and a 2716 he can give any address he wants
or the address resulting from how he connects the 2 ICs. The address then is computed from the bits of A0 to A15 ?

i will try to find a book for 6802/08 programming for better understanding

[Kerry Imming]

2716 is a 64Kbit device, 8K x 8 bits, 13 address bits
2316 is a 16Kbit device, 2K x 8 bits, 10 address bits

If you want more addressable bytes than that you must use multiple
memory devices and select between devices with unused (usually upper)
address bits.

The 6802 processor can address 64K bytes. The choice of RAM/ROM devices
would have been based on cost and availability. As for how the address
range is distributed among devices and RAM/ROM, that is somewhat
arbitrary. ROM would need to be in the upper address space since that's
where the 6802 starts on reset. Other memory would be assigned to
provide future expansion in ROM/RAM size.

- Kerry

[John Robertson]

The advice for the 2716 and 2316 above is incorrect. (sorry Kerry - you
don't make many mistakes!)

They are the same size 2K x 8 or 2K of ram. The 2716 is an EPROM, and
the 2316 is a Masked ROM. The 2316 used in Williams games uses /CE and
/OE the same as a 2716. Bally games were not always the same select logic.

The memory space for the ROMs is defined by the CPU's RESET and NMI
locations - different MPUs look at different memory locations for the
RAM and the ROM. As I recall the 68XX series looks for the RESET vector
somewhere around FFFE and FFFF (two bytes to decode the memory location
in a 16 bit memory space - 64K. So at least one ROM must have a location
at the 'top' of the Memory space so the CPU can find the Reset.

RAM for the 68xx starts at 0000h, so some RAM must be found there for
the CPU to have scratchpad RAM available. After that you can locate the
RAM/ROM anywhere you like, convention has the RAM at the low end, and
the ROM at the high end, then I/O and anything else is in the space not
occupied by RAM or ROM.

[seymour.shabow]

John Robertson wrote:
>
> The memory space for the ROMs is defined by the CPU's RESET and NMI
> locations - different MPUs look at different memory locations for the
> RAM and the ROM. As I recall the 68XX series looks for the RESET vector
> somewhere around FFFE and FFFF (two bytes to decode the memory location
> in a 16 bit memory space - 64K. So at least one ROM must have a location
> at the 'top' of the Memory space so the CPU can find the Reset.
>

The processor doesn't know/care what address ends up at the reset/other
vectors at $FFF8-$FFFF (reset is FFFE-FFFF). The chipset in system 6
lives at $6000-$7FFF in the code itself. Because of the chip selection
it gets repeated up to $FFFF (and likely one intermediate location as
well, where the address bits used to select it also select that location
if requested).

System 7 moved the romspace to the 'real' location its romspace is
$D000-$FFFF.

> RAM for the 68xx starts at 0000h, so some RAM must be found there for
> the CPU to have scratchpad RAM available. After that you can locate the
> RAM/ROM anywhere you like, convention has the RAM at the low end, and
> the ROM at the high end, then I/O and anything else is in the space not
> occupied by RAM or ROM.
>

The Ram can live anywhere in memory as well. It does not have to be in
zero page $00-$FF. There is nothing in the processor startup that
requires ram there. Most people designing systems put ram there as
there are shorter (i.e. more efficient) instructions to take advantage
of it, and most software does use page 0 for scratchpad use, but it's
not required there.

You are likely thinking of the 6502 that MUST have some ram in page 1
$100-$1FF as the stack hi byte is hardcoded to page 1. (System 80's
stack ends up in $100-$17F, so you don't need the entire page populated
with ram) Additionally, it's really useful on the 6502 to have zero
page ram as so many instructions assume zero page access.

[John Robertson]

On 2022/11/16 6:33 a.m., seymour.shabow wrote:
> John Robertson wrote:
>>
>> The memory space for the ROMs is defined by the CPU's RESET and NMI
>> locations - different MPUs look at different memory locations for the
>> RAM and the ROM. As I recall the 68XX series looks for the RESET
>> vector somewhere around FFFE and FFFF (two bytes to decode the memory
>> location in a 16 bit memory space - 64K. So at least one ROM must have
>> a location at the 'top' of the Memory space so the CPU can find the
>> Reset.
>>
>
> The processor doesn't know/care what address ends up at the reset/other
> vectors at $FFF8-$FFFF (reset is FFFE-FFFF).  The chipset in system 6
> lives at $6000-$7FFF in the code itself.  Because of the chip selection
> it gets repeated up to $FFFF (and likely one intermediate location as
> well, where the address bits used to select it also select that location
> if requested).
>
> System 7 moved the romspace to the 'real' location its romspace is
> $D000-$FFFF.
>

Agreed it didn't care what happened outside of the vectors, but as you
had to have memory there it was easier to just stuff all the ROM
addressing in the same area to save on chip selects.

System 3-6 didn't use A15 so the ROM was mirrored to /A15. I assume they
were saving a few pennies for ICs and copper on the PCB traces.

>> RAM for the 68xx starts at 0000h, so some RAM must be found there for
>> the CPU to have scratchpad RAM available. After that you can locate
>> the RAM/ROM anywhere you like, convention has the RAM at the low end,
>> and the ROM at the high end, then I/O and anything else is in the
>> space not occupied by RAM or ROM.
>
> The Ram can live anywhere in memory as well.  It does not have to be in
> zero page $00-$FF.  There is nothing in the processor startup that
> requires ram there.  Most people designing systems put ram there as
> there are shorter (i.e. more efficient) instructions to take advantage
> of it, and most software does use page 0 for scratchpad use, but it's
> not required there.
>
> You are likely thinking of the 6502 that MUST have some ram in page 1
> $100-$1FF as the stack hi byte is hardcoded to page 1.  (System 80's
> stack ends up in $100-$17F, so you don't need the entire page populated
> with ram)  Additionally, it's really useful on the 6502 to have zero
> page ram as so many instructions assume zero page access.

Yes, 6502, the clone of the 6800...opps!

A beginners guide to the Williams 68xx addressing is abuilding...

Shall we go to the I/O next? Although I thinking Blanking is interesting.

[Kerry Imming]

UGGHHH... you're right. I'm not sure what I got when I searched for
"2716 datasheet". Thanks for catching that.

- Kerry