Andre is really getting to them

[Tom Kunich]

I'm told that all the Stupid 5 can do to respond to Andre now is to shout insults which is all of the wits they have left. It is pretty funny that in comparison, penniless paupers and mindless fools, cannot come up with one single contrary fact and so in extremis can only shout names with the effectiveness that usually has given them - none. The walls are closing in and the Stupid 5 grow more and more frantic to make a dent in a piece of steel with their heads.

But it is entertaining to watch idiots attempt to outsmart a genius.

[John B.]

But Tommy I come up with facts.... about your lies.

But you never rebut them so obviously my facts... that you are a lying
piece of shit... must be correct.
--
Cheers,

John B.

[Andre Jute]

You prove Tom's point handsomely, Slow Johnny. He lives in your head, rent-free. After years of your abusive ad hominem, all you can add is more abusive ad hominem. You don't even have the wit to realise Tom is manipulating you like a palm puppet. But don't worry about it. Your block warden, Franki-boy Krygowski doesn't have any answers either, sliding into a tone of resignation and bafflement and repeating himself over and over and over again, just like you.
>
Unsigned because you know who this is. But, hey, thanks for making it so easy to put you down like mongrel dog.
>

[Andre Jute]

On Friday, April 7, 2023 at 1:10:39 AM UTC+1, Tom Kunich wrote:
> I'm told that all the Stupid 5 can do to respond to Andre now is to shout insults which is all of the wits they have left. It is pretty funny that in comparison, penniless paupers and mindless fools, cannot come up with one single contrary fact and so in extremis can only shout names with the effectiveness that usually has given them - none. The walls are closing in and the Stupid 5 grow more and more frantic to make a dent in a piece of steel with their heads.
>
> But it is entertaining to watch idiots attempt to outsmart a genius.
>

Always happy to please the audience according to their desserts. The Stupid Five's patent desperation doesn't give one much confidence in their resilience when the crunch inevitably arrives. But I've always said that their salient characteristic is the nastiness and weakness of their characters, so their current desperation is a natural consequence of their malicious characters. -- AJ
>

[Tom Kunich]

I believe you've hit the target directly in regard that they have no character at all and only maliciousness. It doesn't matter if you're an Einstein or a church Deacon or someone who feels they have never made a single dent in society, we are all equal here. But the Stupid 5 absolutely have to believe that they are superior. To listen to them I started huffing and puffing and telling everyone how great I was when it started with their claiming I had no idea what I was talking about. And a technician with an EE degree, a crew chief on an obsolete bomber which was nothing more than a B29 with different engines and never used for anything other than photo reconnaissance, a TEACHER, a failed politician and some hard scrabble idiot too frightened to use his real name.

Now there is absolutely nothing at all wrong with any of these positions and the very fact that they made a living at it means that they were required. But they were replaceable by dozens of others. As I probably was. But I was there and the replacements weren't and the more experience I gained made it more and more difficult to replace me.

After denying I knew anything the predictions I made from my long term experience turned out to be square on target. And more and more, the prediction that most of the excess deaths presently occurring and increasing, look to be an AIDS-like syndrome from the vaccine appears to be true. Several of the latest papers in scientific and medical journals have strongly hinted at it and mRNA vaccines are now suggested by the CDC to only be used on 75+ year old's with additional serious medical problems.

I was in the middle of the search for the cause of AIDS and people like Liebermann couldn't even get a job in the hottest job market ever. Now people with his attitudes have killed the entire industry in California. I showed all of the instruments I designed and it was obvious because they all used the same keyboard that I designed for the microtitration device. What was left for them to do but to deny it like 6 year old's being beaten at checkers by a 4 year old and throwing all of the checkers on the floor?

They want me to seem the egocentric asses they are and it isn't working because I actually did things and they haven't. I give advice and not commands like Flunky "He isn't a programmer".

Hey Flunky, what is this actually doing?

/*SuperSnoop Dectector Board

Operation of the Detector:

1. Via a Detector wand the board detects current
flow through the water. The current flow is via an AC source from the
Generator Board. This current flow is detected via the voltage drop
through the medium's resistance. It is measure with the 24 bit ADC
(U4) LTC 2440 and passed to the MPU via the Serial Data mechanism on
the C Port of the MPU. This value is saved in a "Latest" and "Last"
Register set to be used for comparison. Port C also exposes the CCP
mechanicm to drive both the LINX_tx and the headset. The LINX mechanism
* only requires only an 800 or 1600 cycle signal that demonstates connections
* to the Generator board. The headset connection is a complex full audio
* sound mechanism that demonstrates both the direction and distance to
* the focus of the currect source.
*
2. Port B is used to to drive informational LED's and to alow in-circuit
programming of the MPU.
*
3. Port D is used exclusively to drive a graphics display (OLED)
*
4. Port A is aso used in the drive of the graphics display as well as
using both Analog inputs. AN0 is used for power detection and AN1 is
used to detect a pitch control to allow the operator to adjust the pitch
to suit his particular hearing.
*
* It is also my intent to use the graphics control to indicate a bar
graph so that you can use that to more closely identify direction of
the currect focus. This may not be possible in the available time. */


// PIC18F45K22 Configuration Bit Settings

// 'C' source line config statements

#include <xc.h>

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1H
#pragma config FOSC = XT // Oscillator Selection bits (XT oscillator)
#pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = ON // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
#pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
#pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2)
#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)


// Definitions

#define testbit(var, bit) ((var & (1 << bit)))
#define setbit(var, bit) ((var |= (1 << bit)))
#define clrbit(var, bit) ((var &= ~(1 << bit)))
#define TRUE 1
#define FALSE 0
#define FAST 1
#define SLOW 0
#define HALF_SEC 500
#define ONE_SEC 1000
#define FUNC_LED 0
#define TRUE_ON 1
#define TRUE_OFF 2
#define uC 0
#define STAT 1
#define BAT_NORM 2
#define BAT_LOW 3
#define SYNC_LOW 4
#define SYNC_HIGH 5

// Variables

char timer3_int; // 125 uSec clk timed out
unsigned char function_timer; // Counts clocks to 1 msec

//--------------------------------------------------------------------------
// variables for the ADC structures and input

long instant_read;
long adc_avg[10];


// pointers for moving ADC data
char measure; // loading data
long measure1; // used for manipulations
long * measure2; // used for cross coupling

char fresh_read_flag = FALSE; // Marks a complete LONG read
char new_reading_flag; // Use to mark latest ADC reading
char byte_count = 0; // Read ADC in Master Mode
char adc_avg_ctr = 0; // Couunts position in string
unsigned char timer3_countL; // Low end timer count
unsigned char timer3_countH; // High end (probably not ness.)
unsigned char blinker_cnt;

//------------------------------------------------------------------------
// Below are the LED variables.


//char uCrunning = TRUE_ON; // Red heartbeat no leak
//char sync = FALSE; // Grn heartbeat and leak
//char power_norm = TRUE_ON; // Grn power OK
//char power_low = TRUE_ON; // Both power low Red power gone
//char pol_low = FALSE; // 800 Hz to LINX_tx
//char pol_high = FALSE; // 1600 Hz to LINX_tx


// Normal pre-load on-off periods in msec

const int led_refill[12] = {500, 1000, 500, 1000, 6, 6, 6, 6, 6, 6, 6, 6};
int led_time[12] = {500, 1000, 500, 1000, 6, 6, 6, 6, 6, 6, 6, 6};
char led_on[6] = {TRUE_ON, FALSE, TRUE_ON, TRUE_ON, FALSE, FALSE};
char where = 0; // Where in the arrays - init to start

//-----------------------------------------------------------------------
// Procedures and functions


void interrupt MyIsr (){

// test for timer timeout
if (testbit(PIE2, TMR3IF)) { // If timer int. kick counter
timer3_int = TRUE; // Kick counter
clrbit(PIE2, TMR3IF); // clear for next timer int
}
// Test for ADC data ready
else if (testbit(SSP1STAT, 0)) { // SPI input register full (BF)
measure = SSP1BUF; // Also clears BF bit
if (byte_count++ == 0)
measure1 = measure;
else if (byte_count++ < 3) { // if not full 32 bits
measure1 = measure << 8 ; // xfer to avg_read pile
}
else {
instant_read = measure1;
measure1 = 0UL;
byte_count = 0;
new_reading_flag = TRUE;
}
}
}

void trans_adc (void) { // Move adc_read to avg_read structure

if (adc_avg_ctr < 10) { // set by interrupt
measure2 = &instant_read;
new_reading_flag = FALSE; // meands that data esd xferred
}
}

void reset_pwm (char speed) { // set bit 0 == /4 prescalar else 1:1

if (speed == FAST)
setbit(T2CON, 0);
else
clrbit(T2CON, 0);
}

void blink_light() {

// bliknk_lights uses a structure "lights" to carry the information
// of whether a light is on, how long it is on and how long it is off
// Intially everything but the uC function light will be a short on
// and off so that when turned on by placing a "TRUE_ON" in the
// hi_lo_on char in the structure for that light it will operate at
// what looks like a continuous "on" at a reduced brightness, power
// level and less likely to overheat. These numbers can be adjusted
// after the unit is operating.


while (where < 11) {
if (led_on[where] == TRUE_ON) {
led_time[where]--;
if (led_time[where] == 0) {
led_time[where] = led_refill[where];
led_on[where] == TRUE_OFF;
setbit(PORTB, (where/2));
}
where++;
}
else if (led_on[where += 1] == TRUE_OFF) {
led_time[where]--;
if (led_time[where] == 0) {
led_time[where] = led_refill[where];
led_on[where] == TRUE_ON;
clrbit(PORTB, (where/2));
}
where++;
}
}
if (where == 11) {
where = 0;
}
}




void main () {

char ad_flag; // Counter


// Initialize PORTs

TRISA = 0b00000011;
TRISB = 0b11000000;
TRISC = 0b00011000;
TRISD = 0b00000000;
TRISE = 0b00001000;

// Initialize the LTC2440 24 Bit ADC

PORTC = 0b00000001; // Bit 0 high = lowest speed conversion A-D

// Intialize MPU Serial Port 1 into Master Mode

SSP1CON1 = 0b00100100; // Slave Mode
SSP1STAT = 0b00000000; // CKP = clock polarity 0->1

// Init ADC structure pointers



// Initialize Timer 3 for 125 uSec to use in counters.
// 10 clocks = 1600 Hz, 5 clocks = 800 Hz
// 1 full cycle of Generator Xmission ~ 2898.55 Clocks

PIE2 = 0b00000010; // Enable Timer 3 Flag
PIR2 = 0b00000010; // Enable Timer 3 Interrupt
IPR2 = 0b00000010; // Interrupt is high priority
T3CON = 0b00000001; // Timer Engabled
TMR3L = 0b01111111; // 125 uSec Clock

timer3_countL = 7; // 1 millisecond timeout

INTCON = 0b10000000; // Turn interrupt on


// Set Data Structure to ALL 1's. Perfect data is zero for
// no leak and low levels for leak but centered wand.


// Initialize OLED
// OLED with be communicated with parallel port for speed


// Intialize CCP2 for PWM to LINX_tx

setbit(TRISC, 1); // CCP2 = Pin RC1
T2CON = 0b00000101; // TMR2 = ON Prescalar = 4
CCP2CON = 0b00000010;

// Iniialize ADC for power level monitor

ADCON0 = 0b00000101; // ADC 1 Enabled
ADCON1 = 0b00000000; // V ref = power and ground
ADCON2 = 0b00111110; //


while (1) {

CLRWDT();

// Count down any necessary timers from interrupt clock
if (timer3_int == TRUE) { // Timer countdowns
if (timer3_countL == 0) {
function_timer--;
timer3_countL = 7; // 1 msec - operate LED's
blink_light();
}
else {
timer3_countL--;
}
}

trans_adc();
// Move immediate reading to averaging structure


// Test and mark battery voltage
// Mask off upper bits of ADRESH

if (ad_flag == FALSE && testbit(ADCON0, 1) == 0) {
setbit(ADCON0, 1);
ad_flag = TRUE;
}
if (ad_flag == TRUE && testbit(ADCON0, 1) == 0) {
if (ADRESH == (0x02 & 0x3F) && ADRESL <= 0xE3 ||
ADRESH < (0x02 & 0x3F) ) {
clrbit(PORTB, 2);
setbit(PORTB, 3);
}
else if ((ADRESH == (0x02 & 0x3F) && ADRESL > 0xE3) &&
(ADRESH <= (0x03 & 0x3F) && ADRESL >= 0x07)) {
setbit(PORTB, 2);
setbit(PORTB, 3);
}
else {
clrbit(PORTB, 3);
setbit(PORTB, 2);
}
ad_flag = FALSE;
}

}
}