I know there are (or have been) some memober with expertise in
HDLs, so I hope there's someone still on the mailing list who can
offer an opinion.
Firstly, what would be a good book (physical, printed, flat dead
tree sort of thing) to learn VHDL or SystemVerilog from?
Secondly, what's a decent set of open source tools that I can use
to play with this stuff, up to and including synthesis? I'm looking at
Yosys, which seems to be able to sythesise for the Xilinx Spartan 6,
which is what's in the SpecNext.
I'm a complete novice at this sort of thing, but I've picked up
some of the basics over the years, down to the logic gate level, and
up to state machines. I feel the need to learn to use the tooling now.
Thanks,
Hugo.
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