Jonathan Harston
unread,Feb 1, 2026, 12:11:39 AM (7 days ago) Feb 1Sign in to reply to author
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to RC2014-Z80
I started sketching something out and it looked familiar. Digging through some old notes I found some notes I'd made on detecting a serial break at the hardware level.
* Serial idle is a constant '1' state.
* A serial frame is a '0' state, followed by up to nine '0' or '1' states, followed by at least one '1' state, then returning to the idle '1' state.
* To send a serial break the line must be held in the '0' state for at least two characters.
So, when no break is being received, the data line is either '1' (idle) or there will be at least one '1' in ten RxClock cycles - either a '1' bit in the data or the terminating '1' bit. When a serial break has been received the line has been held at '0' for at least 20 RxClock cycles.
So, use the RxClock to clock a counter, count up to 16 (nice binary number), resetting if an RxData '1' is received. If you have counted sixteen then you must have received sixteen '0's, so you must have received a break. This diagram probably won't come out right:
+-------------+
RxCLK---->+CLK divide +----> BREAK
RxDATA--->+RST by 16 |
+-------------+
eg 74LS93
Connect BREAK (inverted if needed) to the CPU RESET line,and you have a hardware watchdog triggered by receiving a serial break.