Okay, so a basic version of the Monitor for the 8085 CPU board is now available.
The README.md describes the source files used to build the binary. And the sources are all on GitHub as well.
Instead of branching off yet another set of source files from the Z80 Monitor/Debugger, I decided to resort to conditional assembly instead. This is done using the #define CPU8080 in the source code. The zasm assembler I use supports these types of conditional assembly #defines. If your assembler doesn't then you'll want to manually edit the sources to remove the Z80-specific code.
The 8080/8085 Monitor has a subset of the original functionality. This is mostly due to the differences between the 2 CPUs. I'll add in the input/output commands next. The 8080/8085 does not support the in/out (c) instructions so you can't easily access ports in a "dynamic" way. I'll probably run code in RAM as a workaround.
Note that the 8080/8085 monitor has hardware requirements:
- 16550 UART board (either original or RevB versions)
- RC2014 original 8K switchable ROM board
- An 8085 board
The Pageable ROM board unfortunately doesn't work. The reason is that it does not fully qualify the I/O cycle (with WR or RD) before triggering the 74HC393. As a result, running 8085 I/O cycles (to access the 16550 UART) in combination with memory read/write gets interpreted as a trigger to the 74HC393 and all things go to heck from then on. I spent a day wondering why the 8080/8085 Monitor worked with my Z80 CPU+ board but not with the 8085 board. Only discovered the problem when I swapped in the 8K switchable ROM board (properly hacked for 32KB and 28C256 support).
If you insist on using the Pageable ROM board, you will need to remove the 74HCT138 and 74HC393 devices, then solder pin 3 of the 74HC393 to ground. If you still want a paging capability, use the general purpose I/O pins of the 16550 RevB board to drive the Page line (with proper polarity inversion since those pins are high after reset).
Note to everyone else building boards: please make sure that you fully qualify IO or memory cycles in the following way: IO is qualified by M1, IORQ and either RD or WR. Memory is qualified by MREQ and either RD or WR. Or the law of unintended consequences will make itself heard! :)