FPGA RC2014 using quartus schematic capture

[Mark T]

Experimenting with Quartus schematic capture to see if I could get an RC2014 type system to work without VHDL.

It seems to be fairly easy to include VHDL modules in a schematic capture design like this, but doesn't seem to work to add schematic design files into a VHDL module.

Quartus thows a warning about tristate outputs that don't drive external pins, but its able to synthesize replacement using a selector.

Unfortunately I couldn't see a way to simulate open collector controls for WAIT, INT, NMI and BUSRQ, so I've used a 12 way AND gate for each of these and each module has both input and output for these signals.

If you want to add a new card, copy the empty module folder and rename the folder and the schematic file it contains, then add the new functions required. Then in the backplane module edit properties of an empty module slot and change the name of the module. If the new module needs connections to other modules or connections external to the fpga then you also need to edit the backplane schematic file, and possibly also the top level schematic file.

I'm using a Sainsmart board that has CycloneIV E, so this has enough internal ram for 8K ROM and 16K RAM. It might be able to go up to 16K ROM but I didn't try that yet.

If you try it on a different board or different FPGA then you'll need to change the device type and modify the pin assignments to suit your own board.

You also need to add a ROM.HEX file, intel hex format, into the ROM directory. I tested this using Grant Searles BASIC.hex from his FPGA microcomputer project, I didnt include this in the attached.

It might be possible to simulate other RC2014 modules to aid in testing of a new design before actually committing to lay out a pcb. It should be possible to run the design in ModelSim, but probably need to use the quartus tools to generate VHDL from the schematic capture file first.

Next step for me is to include my SDRAM controller and then create a version of the 512K RAM/ROM board and try RomWBW. But this will be much more specific to the sainsmart board.

Mark

[Richard Lewis]

As far as I'm aware FPGA's generally don't have internal tri-state drivers.

I have a Cyclone V DE10-Nano which has the 5CSEBA6U23I7 and about 5.6 million bits of block memory so I've had no issue instantiating 64K RAM and 32K ROMs. You should be able to see how much block memory is in use via the Flow Summary report. 

My project is based on Grant's original code and written entirely in VHDL and so far I've been able to boot up SCM 1.0 S3 and run basic. Working on CP/M next. I'm trying to make it as generic as possible so it will synthesize on Altera/Xilinx etc so no vendor IP. My project is here: rc2014-fpga

At the moment I'm trying to get acia6850.vhd wired in and it's not working so time for some hardware debugging :(

-Richard

[Bill Shen]

Mark,
It is true that internal tristate bus is not allowed, but as long as a physical bidirectional pin is assigned to a signal, multiple tristate buffers as well as open-collector buffers can tie to that signal.  So you can have wire-OR nINT and nWAIT signals driven by multiple open-collector buffers.

Your schematic is rather complicated.  Altera's schematic is capable of efficient, concise representation of complex circuitry.  Personally, I prefer schematic representation at high level showing the interconnection of major logic blocks.  I redraw your schematic into a simpler form that's easier for me to understand.  It may or may not suit your taste.
  Bill

[Mark T]

Hi Richard,
I know fpga doesn't support internal tristate drivers, but thought it was worth pointing out that the synthesis could handle a tristate bus as a selector, as it makes the schematic design similar to a hardware rc2014. I just couldn't find a better way to handle an open collector wire or control.

Did you try running Modelsim on your design to test the 6850. I was able to use it to debug the sdram driver, it might take a few minutes to simulate a few seconds of the simulation. Is it the same 6850 vhdl that I used? I think the enable was positive logic instead of negative logic that I expected on a real 6850.

I think cyclone iv only has about 32k x 9 internal ram.

I didn't try to avoid the altera ip as I thought the schematic entry would be altera only.

I've had Grants design running using vhdl but just wanted to try and do it with schematic capture. Using quartus 13 to support the cyclone iv, not sure if it's been improved in later versions but finding schematic entry very clunky compared to pcb schematic entry with eagle.

Mark

[Mark T]

Thanks Bill, I'll take a look at that tomorrow, I don't dare open quartus at this time or I'll be up all night.

I was just trying to make it replicate the modular structure of rc2014.

[Richard Lewis]

Hi Mark,

Yep, I had my logic inverted (especially the reset pin). Reminded me of an old British science fiction movie: Doppelgänger 

My goal is to replicate Grant's design but using only open source cores. Being a software engineer and not an electrical one, VHDL still seems easier to me than schematics however your schematic (along with Bill's rearrangement) helped immensely. 

I feel your pain with regard to opening Quartus late at night, it's 12am in California now...

-Richard 

[Bill Shen]

Altera's tool allows you to mix schematic, verilog, vhdl, and ahdl in a design.  Their schematic capture is really good and I find myself designing more and more in schematic rather than verilog.  Somehow I understand a design quicker when it is in a pictorial form--sounds like a personal problem ;-)
  Bill

[Mark T]

Hi Bill,

I took a look at your example, it was helpfull to see the OPNDRN primitive used, a quick test adding a second ACIA and looking at RTL viewer seems to confirm it does what I wanted. I'll try putting that into my own version to confirm it works as intended. The reason I didn't try that was I wasn't sure how to include a pull up to logic high if none of the OPNDRN were active.

Creating symbols is easier than I thought it might be. I see the advantage that there is no need to mess about with conduits that are required when using blocks. It does seem to mean that after every change to a schematic file that the symbol file needs to be manually created. When I added the second ACIA it had connections in different positions on the symbol, so I couldn't just copy the ACIA and connections in the top schematic and just swap the ACIA, I also had to rearrange the connections. I couldn't see an obvious way to control the position of inputs and outputs on the symbol, I guess its dependent on the position of the pins in the schematic of the block. I might give that a try.

With PCB design I usually avoid using bus connections and draw it in similar fashion to your quartus schematic example, in my opinion its clearer than using a bus, especially if every signal is connected into the bus and the bus goes everywhere on the schematic as I've seen in a few designs recently. In this case I drew the backplane schematic with data bus, address bus etc, as it seemed to me to represent the RC2014 backplane better. Also it was easy to copy and paste extra empty modules onto the end of the bus, although setting up the connections for n_INT[12..0] etc was a pain.

I might have created the backplane in VHDL if there was an easier way to include schematic entry modules into a VHDL module. It seems to require converting the schematic blocks into VHDL, which would be a manual process after every change to a schematic. I think VHDL is better when a large number of blocks are similar but need different instances.

The other case where VHDL seems to work better is if its not obvious how to reduce the logic, for example a large CASE/WHEN could list every input byte and the required output and then let the synsethesizer take care of the logic reduction.

Even using schematic entry I still find looking at RTL viewer a good test to make sure it generates what was intended.

I used a separate top level schematic to contain the backplane, to select which pins needed to be mapped to physical connections of the FPGA. Then I could leave the pin connections in the backplane schematic that would be usefull to run Modelsim. It also gives an option to have different top level to map to other FPGA devices, but only maintain one backplane design.

Mark

[Bill Shen]

Altera tool does do logic reduction such that the unused gates and flip flops are optimized out.  This can be a problem when run simulation because the particular logic node may have been optimized away.

There are things verilog/vhdl particular well suited like state machine and table lookup. I was just redesigning the BCD to 7-seg display, 7447, and I'm certainly not doing the decoding logic in schematic!

If you've modified a symbol, then it is necessary to regenerate the symbol and rewire the signals in correct order, but if you are just moving the inputs outputs positions, it is not necessary to regenerate the symbol.  There is also a symbol editor you can use to edit the default symbol.

There are many tricks with the schematic editor to speed up the designing process.  The unlimited 'undo' is a powerful feature; cut & paste can be exploited relentlessly; signals and buses do not need to be labeled; all primitive gates and flip flop can connect to bus, so you can draw array of logic very efficiently (for an example, you can represent n-stage shift registers with one FF symbol); you can use the 'Use Rubberbanding' option to your advantage.   It is fun to play with the schematic editor, don't do it late at night, you may never go to sleep!
  Bill

[Mark T]

I was still having trouble with WAIT, NMI and BUSRQ, as these are intended to be driven by open drain but none of the existing modules contain open drain buffers to drive these signals. I couldn't find an equivalent to a pull up resistor, so they were being held logic 0, which then caused the whole thing to be reduced to zero logic used. Workaround seems to be to drive these from an OPNDRN buffer with the input of the buffer held high. This also seems ok on the INT line which is also connected to two ACIA modules.

I have Modelsim running, just a very simple test bench that provides clock and reset and shows address, data and control lines. It looks like it's executing code from the rom.hex file, so I can start to experiment.

The T80 core doesn't seem to be cycle accurate to the z80, but might be due to the parameter settings I'm using.

Mark

[Alan Cox]

> The T80 core doesn't seem to be cycle accurate to the z80, but might be due to the parameter settings I'm using.

With the right settings it should be exact. The only differences I
know of between a modern T80 core and a real Z80 are really obscure
ones (notably LD A,R when R is 0 does not set Z, the rest being
seriously obscure undocumented flag bit stuff)

There is a generally faster but not cycle equivalent core NextZ80
which doesn't have all the weird Z80 undocumented flag effects and the
like but is about four times as fast at the same clock rate.

Alan

[Bill Shen]

I have not heard of NextZ80.  Just downloaded it and it is quite interesting.  I have an old Altera Stratix 1S25 board that I purchased from Parallax in early 2000's.  I think I'll port it and see if I can run some CP/M programs with NextZ80.
  Bill

[Mark T]

T80 runs at 150 MHz, which would make Next80 equivalent to 600MHz, so that's definitely an interesting experiment.

Mark

[Bill Shen]

Have it running at 20 MHz putting out a "Hello World" to the console.  Not bad for a night of work, I'm calling it a night.
  Bill

[Richard Lewis]

Have a look at the A-Z80: A-Z80: An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

It's supposed to be "gate accurate" representation of a Z-80 reverse engineered from the actual chip. A Z80 From the Ground Up

I'm going to have a look at it this weekend. 

-Richard

[Mark T]

I've altered the parameters for T80, but there are still some timing differences compared to a real Z80. This is related to T80 being designed to run in FPGA where all outputs are registered to the rising edge of the clock, while a real z80 has some signals registered to the falling edge, for example /WR, /RD and /MREQ.

I've also tried the AZ80, and this seems to be closer to the Z80. /M1 registered to rising edge of CLK, then /MREQ and /RD registered to falling edge of CLK.

It looks like I still need to make changes to the memory interface for the AZ80 as it doesn't seem to be reading the program correctly.

T80 is probably the better option to run in an FPGA, but as I'm interested in using this to simulate CPLD or discrete logic modules in Modelsim  then I'll probably try to get AZ80 working correctly.

T80 or AZ80 would probably both need a large number of wait states to address external memory or input/output modules if they are running at higher clock speeds.

AZ80 also seems to use less resource within the FPGA.

T80 summary:-

+--------------------------------------------------------------------------------------+
; Flow Summary                                                                         ;
+------------------------------------+-------------------------------------------------+
; Flow Status                        ; Successful - Wed Mar 13 12:33:31 2019           ;
; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name                      ; RC2014_FPGA                                     ;
; Top-level Entity Name              ; RC2014_FPGA                                     ;
; Family                             ; Cyclone IV E                                    ;
; Device                             ; EP4CE6E22C8                                     ;
; Timing Models                      ; Final                                           ;
; Total logic elements               ; 2,554 / 6,272 ( 41 % )                          ;
;     Total combinational functions  ; 2,492 / 6,272 ( 40 % )                          ;
;     Dedicated logic registers      ; 492 / 6,272 ( 8 % )                             ;
; Total registers                    ; 492                                             ;
; Total pins                         ; 34 / 92 ( 37 % )                                ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 196,608 / 276,480 ( 71 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % )                                  ;
; Total PLLs                         ; 1 / 2 ( 50 % )                                  ;
+------------------------------------+-------------------------------------------------+

AZ80 summary

+--------------------------------------------------------------------------------------+
; Flow Summary                                                                         ;
+------------------------------------+-------------------------------------------------+
; Flow Status                        ; Successful - Wed Mar 13 12:54:09 2019           ;
; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name                      ; RC2014_FPGA                                     ;
; Top-level Entity Name              ; RC2014_FPGA                                     ;
; Family                             ; Cyclone IV E                                    ;
; Device                             ; EP4CE6E22C8                                     ;
; Timing Models                      ; Final                                           ;
; Total logic elements               ; 2,073 / 6,272 ( 33 % )                          ;
;     Total combinational functions  ; 1,985 / 6,272 ( 32 % )                          ;
;     Dedicated logic registers      ; 497 / 6,272 ( 8 % )                             ;
; Total registers                    ; 497                                             ;
; Total pins                         ; 34 / 92 ( 37 % )                                ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 196,608 / 276,480 ( 71 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % )                                  ;
; Total PLLs                         ; 1 / 2 ( 50 % )                                  ;
+------------------------------------+-------------------------------------------------+

Mark

[Mark T]

OK so that was a stupid mistake, I was connecting data of the AZ80 to the address bus instead of the data bus.

Now it seems to be running the correct code.

It still has a larger number of warnings in quartus, 1377 compared to 30 for T80.

Still shows lower usage of FPGA resource.

+--------------------------------------------------------------------------------------+
; Flow Summary                                                                         ;
+------------------------------------+-------------------------------------------------+
; Flow Status                        ; Successful - Wed Mar 13 13:35:05 2019           ;

; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name                      ; RC2014_FPGA                                     ;
; Top-level Entity Name              ; RC2014_FPGA                                     ;
; Family                             ; Cyclone IV E                                    ;
; Device                             ; EP4CE6E22C8                                     ;
; Timing Models                      ; Final                                           ;

; Total logic elements               ; 2,103 / 6,272 ( 34 % )                          ;
;     Total combinational functions  ; 1,992 / 6,272 ( 32 % )                          ;

;     Dedicated logic registers      ; 497 / 6,272 ( 8 % )                             ;
; Total registers                    ; 497                                             ;
; Total pins                         ; 34 / 92 ( 37 % )                                ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 196,608 / 276,480 ( 71 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % )                                  ;
; Total PLLs                         ; 1 / 2 ( 50 % )                                  ;
+------------------------------------+-------------------------------------------------+

Mark

[Alan Cox]

> T80 or AZ80 would probably both need a large number of wait states to address external memory or input/output
> modules if they are running at higher clock speeds.

Or a cache. SocZ80 has a dual ported cache and DRAM controller. A
somewhat extreme arrangement 8)

Alan

[Mark T]

I was planning to use Modelsim to test a couple of different ideas for a cache, but intending to build in actual hardware for a real z80 to play with multiprocessing ideas.

Using a CPLD, two off dual port RAM and 40 pin DIP Z80 seems to be feasible to fit in a standard RC2014 size module, although the routing complexity may be a bit high for double sided PCB.

Cyclone IV seems to have enough internal logic to support two AZ80 cores, and there should be enough left over for cache and boot rom, using the external SDRAM

Mark