Fix for CF Card Modules with incomplete address decoding

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positron (Jose L. Collado)

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Mar 9, 2020, 11:34:01 AM3/9/20
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It was mentioned in other topic that the official CF Module has incomplete address decoding, resulting in "ghosting" in upper addresses.
 
I built karlab's 10d CF Module design that also has the same issue. Since it has a pair of unused OR gates, I plan to include A7 in the mix, ORing it with \IOREQ before feeding it to the '138, so only low A7 addresses will activate the module eliminating the ghosting issue.

Does this make sense, or is there an easier solution ? I'm looking for the tightest addressing possible because I'm planning to add some custom modules to my SC-126, that has C0-FF already used for internal peripherals, apart from other cards in the bus (PIO, CTC, TMS9918A, YM2912, etc.).

Thanks in advance for your ideas & replies.
Cheers, JL.
 

Jim McGinnis

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Mar 9, 2020, 12:04:36 PM3/9/20
to RC2014-Z80
Hi Jose Luis!

Check out this potential mod for the RC2014 Cards - it tightens the addressing to only what is required to talk to the board...
I modified and tested this change and it works well.




Jim McGinnis

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Mar 9, 2020, 12:08:20 PM3/9/20
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JL:
I am not sure about a similar cheap fix for the 10d card. It could be equally as simple.

Jim

Bill Shen

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Mar 9, 2020, 12:20:11 PM3/9/20
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Jose,
!IORQ to pin 5 of 74HCT138 is unnecessary, so you can just cut the trace and wire A7 to pin 5 of 74HCT138.  This actually improves the setup time from CF chipselect to read/write.
  Bill

karlab

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Mar 9, 2020, 12:34:20 PM3/9/20
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Hi

I have been working on an improved CF module.

This module can be equiped with an octal bus retriever (HCT245) or putting resistors on the data lines.

The module has also a much tighter IO address.

The module hasn't been tested yet, I am awaiting for HCT245 to arrive in post.


The limitation using CF in our systems; its a hack. 

The CF cards are 16 bits and all the control lines are not handled properly.

For that we need an IDE controller.


It should be possible to use all 16bits but then some multiplexing circuit needs to be implemented and

the code needs to be rewritten.


If/When CF cards do not work very well it is often due to tolerance issues and not to the card or circuit itself.

I have tried to connect the CF card with a ribbon cable, that doesn work well.


Karl


IMG_1580.JPG

positron (Jose L. Collado)

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Mar 9, 2020, 3:01:59 PM3/9/20
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Thank you all for your great responses !

@Bill, I think your solution is valid if I put the jumpers in the \IORD & \IOWR positions (RD & WR been ANDed by \IORQ) . Am I right ?

Cheers, JL.

Jose Luis Collado

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Mar 9, 2020, 3:31:26 PM3/9/20
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... sorry, i meant  RD & WR been ORed by \IORQ...

Saludos,
José Luis.


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Tadeusz Pycio

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Mar 9, 2020, 4:03:45 PM3/9/20
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This module can be equiped with an octal bus retriever (HCT245) or putting resistors on the data lines.

Hi, Karl

I got the best results on HC, not HCT.

PS. The package with classic arrived, thank you.

Bill Shen

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Mar 9, 2020, 7:25:03 PM3/9/20
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Jose,
The CF interface design I have in mind looks like the attached schematic.
  Bill


On Monday, March 9, 2020 at 1:31:26 PM UTC-6, positron (Jose L. Collado) wrote:
... sorry, i meant  RD & WR been ORed by \IORQ...

Saludos,
José Luis.


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CF_XF_scm.pdf

Bill Shen

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Mar 9, 2020, 10:02:05 PM3/9/20
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Karl,
When I run into CF interface problem, putting a RC filter (100 ohm, 100pF) in IORD line is the first thing I'd try.  After that I put 100 ohm resistors in the data lines.  You may  remember the first picture which is my modification to your CF board which is RC filter for IORD.  It is also fairly simple to remove the data pins and replace with 100 ohm resistors as shown in the 2nd picture.
  Bill
CF_modification_for_MB020.jpg
Tiny68K_rev1_CF_mod.jpeg

Bill Shen

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Mar 9, 2020, 10:16:51 PM3/9/20
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Karl,
Z80 is very robust with respect to CF interface.  I find I only need to delay nRD and nWR by one clock and don't really need data lines and IORD terminations which is what I did in Z80SBC64 and Z80MB64.  Both designs can handle every brands of CF disk I tried at 22MHz CPU clock.  680x0 is a lot more problematic.  I need all the data/control terminations plus one clock delay for nRD and nWR at the beginning of an access AND generate necessary hold time at the end of the access.  The 9pcs 100 ohm SMT resistors plus 100pF capacitor is standard in all my 680x0 designs.

  Bill

On Monday, March 9, 2020 at 10:34:20 AM UTC-6, karlab wrote:
MB012_CF_termination.jpg

Jose Luis Collado

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Mar 10, 2020, 8:16:28 AM3/10/20
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Bill, spot on. Thanks, this is the easiest fix for the 10d module that has a '32 in addition to the '138.

Cheers, JL..


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