On Thursday 4 April 2024, Keith S wrote:I've been putting together a 8085 based system using the backplane pro, the 8085 cpu card and memory module card from Phillip, the Tynemouth 68B50 card and the CF v2.0.Burnt the 'rc2014-8085cf-cpm22.hex' file into a 27C256 (and verified it). Formatted a blank CF card as FAT32. Then connected to the ACIA using Putty from a PC at 115200 baud.So far, there has been largely no signs of life, but every now and then I get a tantalising message 'Bdos error on A: Select. ANd one an 'Exit from CP/M'. So something's working (including the serial link).The LED on the CF card rarely comes on, and the tx/Rx leds on the ACIA never do (should they?)
From what you're describing, it sounds like you have a marginal power source.The 8085 CPU will not run off a USB power supply at all. And this would be compounded by the presence of the CF Module (and potentially the APU Module, if it was inserted).For reference I'm using the Backplane-8 with a 1A 7805 replacement device. For the PRO Backplane to use a 2A 5V wall-wart would be my suggestion.
Once you can see something like that, then you can insert the CF Module (or IDE Module if you used the ROM for that instead).
Good point about the power supply. I am using an Apple ipad USB supply capable of some 2A to power the board via the barrel jack. Looking at the VDD line with the scope (C4 in the pic below) , with the CF card connected its about 4.95v mean, or 5.04v with the CF disconnected. The peak to peak value is~2.4v in both cases, i.e. the supply is about 5v +/- 1.2v, or dips down to 3.8v minimum at or around the clock frequency. I wonder if that's enough to prevent a 5MHz 80C85 from working correctly?


Thanks, I'll try adding decoupling to see if I can reduce the noise. I did try removing the CF card, made no difference to how it is behaving, but it didn't change the noise much either.Can you say anything about the INT signal? I'm assuming this is generated by the 68B50 every time it's received a character, would that be correct? And so it should go low (as I'm seeing it does, ~5us after a key press) then go high after the interrupt has been serviced (about 10us later). The fact that its going low/high erratically at first (a bit like key bounce) doesn't seem right to me.
Thanks, I'll try adding decoupling to see if I can reduce the noise. I did try removing the CF card, made no difference to how it is behaving, but it didn't change the noise much either.Can you say anything about the INT signal? I'm assuming this is generated by the 68B50 every time it's received a character, would that be correct? And so it should go low (as I'm seeing it does, ~5us after a key press) then go high after the interrupt has been serviced (about 10us later). The fact that its going low/high erratically at first (a bit like key bounce) doesn't seem right to me.
So I soldered 6 x 10uF tantalums onto the backplane, one every other slot. That does seem to have cleaned up the INT signal; it now goes low after a keystroke and stays low for the 10us or so. Key presses are echoed as before so I believe the ACIA is working OK (yes I had removed the 5v link).One interesting fact: if I type 'cpm' I get a response:
cpmrc= FR_
Just those characters, and it's reproducible -every time. Mean anything?
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Getting somewhere!I replaced the OKI M80C85A with an Intel 8085A. Now I see a welcome message on reset. There is something odd about the terminal, it's like its running at 110 baud or less, as its very, very slow.So I can conclude that the OKI 80C85 was just not up to running at 7+ MHz, or maybe noise on the supply was causing issues, but the Intel part can handle it. The clock waveform is cleaner too.Keith

Those repeated prompts were just me hitting 'return' a few times!I measured the current consumption with the 80C85, it was 120mA, that's including the cpu board, memory board, CF board and ACIA board. Nothing really - I did try running on a 3A stabilised supply which made no difference. I guess the nmos 8085 will consume a bit more, but still well within the 11W (over 2A) the iPad supply can give.Yes, 'cpm sys.cpm' works as expected. A 'dir' listing takes about 10s to complete, which seems slow for 115200 baud, but then maybe that's all an 8085 can manage?
Some CPM commands hang and/or give errors (ls gives a 'Bdos error on @: Select' error, then it sits for a while with the CF led flashing for a minute or so before coming back to the prompt.). So still not 100%.
It should be equally fast as the Z80 version. If not there’s still an issue lurking.
Your listing looks good though. So I’m a little confused as to why it might be behaving “slow”. Very odd.
I just noticed the clock on the 8085 is running at about 120KHz!This is with the Intel nmos 8085. Fortunately, I have a couple of OKI 80C85's, one of which I tried before. So I tried the other and... 7.3728MHz clock, and, the speed of test scrolling etc is comparable to the z80 version!I wonder why the Intel chip was oscillating at 120KHz even with the same 14.7456 crystal. Maybe it was a faulty part. Anyhow all seems to be working now, thanks for the all the advice, it's always worth assuming nothing!
For NMOS parts, you don't need load capacitors on the crystal...
USB chargers are frequently crap, and do very poor job of power filtering. Get a regular switch mode 5V power supply.... These are frequently used for home network equipment (switches, small routers)



NMOS and TTL outputs might not be compatible with CMOS inputs (74HC). If using NMOS and TTL better use them with 74HCT CMOS ICs
-- Sergey
On Friday, April 5, 2024, Keith S wrote:The power supply p/p variation was still about 1.25v with the working 80C85. But that's well within the operating limit in the spec of 3-6v.
In all cases there's only a few mV of noise on VCC.So I'd be quite worried about a power supply for m system that was providing an unstable 5V, particularly one that had a +/- 1 V variation!
On Monday, April 8, 2024, Phillip Stevens wrote:In all cases there's only a few mV of noise on VCC.So I'd be quite worried about a power supply for m system that was providing an unstable 5V, particularly one that had a +/- 1 V variation!I've measured ripple using a Keithley 2231A 5V, 3A stabilised power supply and the board level ripple was not that much different. Actually Apple USB chargers are well designed, and have low output switching noise (in the tens of KHz range). The same cannot be said for generic chinese USB chargers which can have 3x the ripple.
The measurements I made showed the ripple issue was not from the SMPS, it was generated by switching at the clock frequency at 7.3MHz, not kHz. There are 3 possible causes.
1) insufficient decoupling cap on board2) Inductance in the supply leads causing L * di/dt drop3) Fast edge rates aggravating (1) and (2).The decoupling cap on the backplane being augmented by adding 10uF tantalums helped a bit, I'd like to see more onboard decoupling too to address (1).
For (2) wider power/ground traces on the backplane would help, or a 4 layer board with 2 being used for VDD and GND.
For (3) using not the fastest buffers may help, when those big octal buffers switch they are probably the source of the noise. When I was designing 74F logic at Fairchild many years ago we have to limit the slew rate of the output buffers as othewrwise the fast edge rates caused a lot of supply noise problems compared to older 74LS. So using AHCT instead of HCT may not be a good idea.
A fourth option is that I'm not seeing the noise because my 60MHz 'scope is too slow.
I don't think it would make too much difference at 7MHz, but the technical marketing material for the AHC(T) logic family does emphasise the slower skew rates of their products, which are designed to eliminate ground bounce and electrical noise. Their higher final speed (relative to HC(T) is achieved by faster internal gates, which allow the output skew to be kept quite slow with relatively low (8mA) drive. But that is technical marketing material that I'm just regurgitating, and I have no tools to analyse the actual nanosecond skew rates properly. So, IDK...???
On Monday, April 8, 2024 at 10:39:46 AM UTC+1 Phillip Stevens wrote:I don't think it would make too much difference at 7MHz, but the technical marketing material for the AHC(T) logic family does emphasise the slower skew rates of their products, which are designed to eliminate ground bounce and electrical noise. Their higher final speed (relative to HC(T) is achieved by faster internal gates, which allow the output skew to be kept quite slow with relatively low (8mA) drive. But that is technical marketing material that I'm just regurgitating, and I have no tools to analyse the actual nanosecond skew rates properly. So, IDK...???
Be careful, the datasheet 'skew' is the difference in delay times between one buffer and another; that's not the same as slew which is the voltage swing of an output divided by its transition time (i.e. dV/dt). The data sheets don't give the latter alas, some give the transition time, from which you can deduce the slew rate, some don't. For example the TI SN74HCT240 has transition time of 8nS typical at 25C, 4.5v into a 50pF load. The SN74AHCT240 datasheet does not mention transition time alas. But given that the AHCT propagation delay is about half that of HCT, I'd expect the slew rate to be higher, although maybe not by 2x.
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That's very interesting, Phillip, I've not seen that before. Do you have a link to that document?
Looks like AHCT and HCT have very similar slew rates, whereas AC are around double, which would make them worse for a noise perspective..
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