Diagnostic module for RC2014

[Bill Shen]

This is a continuation of CPLD diagnostic board mentioned in Jan 28 under the topic of "Desperately seeking..."  I felt it has enough potential to merit its own topic.

The idea is a simple logic analyzer that displays the contents of the RC2014 bus as it power up.  To do that the values of addresses, control, and data are sampled and transmit out via a serial port at high speed, while the processor is running very slowly.  How fast the serial and how slow the processor? The modern PC should be able to receive 460K baud without hardware handshake; since there are 4 bytes of serial data (2 byte address, 1 byte control, 1 byte data), it takes 86uS to transmit 4 bytes at 460K.  Z80 executes an instruction in 2 clocks minimal (M1 cycle), so the clock can't be faster than 86uS/2 or 43 uS or 23KHz.  Let's pick CPU clock of 19.2KHz because that means the serial port will operate at 300 baud.

The logic for such analyzer is fairly simple, consists of 4-input byte-wide data mux feeding to a 10-bit shift register that sends 1 start bit, 8 data bit, 1 stop bit at 460K baud.  There is a simple state machine to start transmission with MREQ or IORQ asserted and halt when all 4 bytes are transmitted.  It should easily fit a CPLD like EPM7128, and probably will fit a smaller CPLD like EPM7064 in hobbyist-friendly 44-pin PLCC package. 

Large amount of data will be logged on the PC side.  Four bytes of binary data per instruction fetch adds up to a lot of data in very short amount of time.  I read about Z80 protocol decoder by hoglet on stardot.org.uk and that may be useful in converting raw data back to instruction stream.

I have a RC2014 prototype board that maybe suitable for experimenting.  https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:protorc3

  Bill

[Randy Mongenel]

Couldn't this be done with the z80ctrl board from JB Langston?

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[Zorak]

Awesome idea Bill.  There is a great body of work done in military systems for PM/FL - Performance Monitoring / Fault Localization which does this.  In military systems the hardware (latches and shift registers) is built into many ICs.  Good luck.

=Steve

[Bill Shen]

From what I know of z80ctl is it assumes the system is working at some level because it interacts with the processor & memory.  The diagnostic board simply monitor and spitting out data as it see.  It is pretty easy to build, cheap and may be attractive to people wanting to experiment with CPLD.
  Bill

[Steve Markowski]

Got it.  Thanks for the  clarification.  =Steve.

[Bill Shen]

Here is the diagnostic module plugs into Z80MB64.  The diagnostic module is basically a CPLD (Altera EPM7128S).  The oscillator is removed from Z80MB64 and plugs into the oscillator socket of the diagnostic module.  It outputs serial data to console at 460K baud while driving the processor on Z80MB64 at 1.8 Khz.  Every bus transaction is captured and displayed on console.  The display is 2 bytes of addresses and 1 byte of data in ASCII format followed by carriage return. 

The following screenshot shows the output corresponding to console polling program.  The refresh cycle is confusing, it may be more readable by filtering out the refresh cycles.

  Bill

-------------------------------------------------------

0000BB71                     A     1202 cinq:    
0000BB71 DB F8               A     1203     in a,(0f8h)    ;read status
0000BB73 E6 01               A     1204     and 1        ;data ready flag is in D[0]
0000BB75 28 FA               A     1205     jr z,cinq
0000BB77 DB F9               A     1206     in a,(0f9h)    ; read data
0000BB79 C9                  A     1207     ret

[Bill Shen]

The RC2014 diagnostic module above is based on EPM7128SQC100 which may be difficult to assemble.  The CPLD design does not require EPM7128S, it will also fit a EPM7064S in PLCC44 package.  Such EPM7064-based board is probably half the size of the prototype board pictured below.

There is another diagnostic application for the CPLD module; the CPLD has enough logic fabric to emulate a small ROM, probably about 30-50 bytes.  That should be enough to boot up Z80, test RAM, possibly initialize SIO.  It can transmit status info via the serial port in CPLD as it test RAM & SIO.  This test can run at full speed (7.37MHz). 

  Bill

[Greg Holdren]

Bill,

Nice to know about the size of the design. I was going to ask how much of the 128 it used. I was thinking on doing something similar on my Xilinx 9572/95108 board. I'll try to translate your design into the Xilinx ISE tool and see how it goes.

Greg

[Bill Shen]

Greg,
The limitation is mostly in the I/O pins.  PLCC44 is 1 pin short, so I rob M1 signal to make it work.  Attached is the schematic of the serial transmit
  Bill

[Bill Shen]

I tried the idea of embedding ROM code in CPLD so CPLD can serve as a boot ROM with diagnostic capability.  I'm surprised to find that I can embedded 128 bytes of ROM code in a small EPM7064S CPLD.  So here is the setup in the picture:
* A diagnostic board with EPM7064S PLCC44 CPLD that contains 128 bytes of boot ROM and a serial transmitter operates at CLK/16 baud, N-8-1.
* A Z80 CPU board.

Z80 boots off the ROM inside CPLD which first prints out a sign-on message, then initializes RAM at 0x8000 (there are no RAM in this setup), verify it to see if RAM OK; prints a corresponding message, then initializes SIO at 0x80 and sends a character out of SIO.  Test repeats.  Program is 120 bytes long.  This is a screen shot.  Program is cross assembled (I use ZDS v3.68) and the machine code manually copied to a Verilog lookup table (Z80ROM.v) that is compiled into CPLD programming file.  This part is tedious, but it should be possible to automate with a script.

To summerize, the diagnostic module is a simple board consists of a PLCC44 CPLD, CPLD programming header, optional oscillator and a serial port.  Two types of diagnostic can be programmed in the CPLD thru the programming header:
1.  A logic analyzer that captures address & data of every Z80 memory and I/O transactions and output them over the serial port.  The processor is running very slowly (about 2KHz) so not to overrun the serial port transmit.  The CPLD generates the slow processor clock, so the existing clock module must be removed.
2.  A bootstrap diagnostic board that replaces the existing ROM board.  The CPLD contains 128 bytes of bootstrap code that signs on, tests memory, initializes I/O, and sends data out of the initialized I/O device.  In every stage, the diagnostic board also outputs corresponding messages out of its own internal serial port.  It runs full speed in this mode of operation.

It is also fun to experiment with CPLD.  The development tool is free downloadable, the programmer is lesser than $5 and part (EPM7064SLC44) is about $3-$4 each from UTSource.
  Bill

[J.B. Langston]

z80ctrl can be configured to single step the clock and output the raw values observed on the bus.

[J.B. Langston]

And also to write and dump memory and I/O locations.

[Bill Shen]

Revisit the logic analyzer function:  I eliminated the display of refresh cycle so it is easier to read; For write operation, I also delay the capture of data until write strobe is asserted so valid data is displayed.  Now the display is more readable.  Attached is the data captured by the logic analyzer for the serial port polling routine:

0000BB7A                     A     1195 cinq:    
0000BB7A DB F8               A     1196     in a,(0f8h)    ;read status
0000BB7C E6 01               A     1197     and 1        ;data ready flag is in D[0]
0000BB7E 28 FA               A     1198     jr z,cinq
0000BB80 DB F9               A     1199     in a,(0f9h)    ; read data
0000BB82 C9                  A     1200     ret

The design fits in a EPM7064S, just barely; the pin utilization is 100% and 97% of logic are used.  Too bad, it will be nice to display additional info like memory or IO read/write and a microsecond time value.  EPM7128 is capable of these additional features, but not EPM7064.

This is useful enough that I'll design a diagnostic board based on EPM7064.  It is likely a $10-$15 kit.  I also attached the Altera CPLD design for those interested.
  Bill

[Greg Holdren]

Bill,

That is neat. I would not think it would be possible to embed 128 bytes in a 7064. But there you go. 

Greg

[Bill Shen]

Greg,
That's a serial port transmitter, decoding logic for ROM, serial port AND 128 bytes of ROM in a 64 macrocell CPLD. Yes, I'm quite surprised by that as well. I would have been pleased with 32 bytes of ROM.

As much as I have used CPLD, this changes how I think about bootstrapping. ROMless designs that pull data in from CF, SD, serial EEPROM, or serial port are entirely do-able with 128 bytes of bootstrap ROM.

I can also see a "universal CPU tester" with a CPLD and an oscillator; program the CPLD for a particular processor, plug in the processor and it will exercise some of the instructions and transmit a status. There are so many cheap processors on eBay, would be interesting to get some to run the tests.
Bill