I've finished the assembly diskio components which run under the ChaN FatFS system to provide an interface using the Intel PIO8255. AA is helping to get the ChaN FatFS code added to z88dk as a third party library.
TLDR; it won't be long before a full FatFS (including exFAT and LFN) is available for rc2014 via z88dk.
TLDR; it won't be long before a full FatFS (including exFAT and LFN) is available for rc2014 via z88dk.
I've finished the assembly diskio components which run under the ChaN FatFS system to provide an interface using the Intel PIO8255.
AA is helping to get the ChaN FatFS code added to z88dk as a third party library.
TLDR; it won't be long before a full FatFS (including exFAT and LFN if desired) is available for rc2014 via z88dk.
I had a quick look at the ROMWBW mapping, and it is essentially similar. Port A and B for the I/O, and Port C for the control lines. The only difference is which control line is attached to which 8255 pin.
The important thing is that only three IDE interface control pins are NOT passed through an inverter. These are the address pins DA0, DA1 and DA2. All other pins have to pass through an inverter, so that they "rest" in high state. They need to rest in high, so that when the interface is swapped from Read to Write, and back, they don't reset the disk. The 8255 sets all pins to Logic 0 when it changes modes, this is a bug / feature of the chip.
I chose to use the three pins for the address lines that are also used for input in Mode 1 and Mode 2 of the 8255. These pins are not passed through the inverters, so they can actually be used as inputs and the interface remains general. If they were passed through inverters, they would be unusable as inputs to the 8255, and therefore Mode 1 and Mode 2 wouldn't work.
Bottom line is that the pin selection I've made is more general than that chosen by others, so that the IDE pinout can be used for other purposes, as well as just for a disk drive. I'm planning in the long term to use the 8255 as an extension interface for other boards or interfaces, using the IDE 44pin cable and 2mm pins because they're very neat and easy to obtain, and cheap.
At the end of the day it makes very little difference (if you don't care about generality for the 8255), because the pin selections are mapped by definition, and it doesn't make any real difference. The code will work on all the interfaces just by changing a define.
I got my 82c55s from Digikey. They're "off the rack" in PLCC format. Not DIL, but the socket is still through hole.
Thanks, It is all working fine now. Probably not going to put FatFS into z88dk, because it is very configurable and any configuration decision would probably be the wrong one for most people.
I was looking through the RomWBW source, I see that has support for IDE drives driven by the 8255 on the SBC-v2 and Zeta boards, but the port / signal mapping looks a bit different (https://github.com/wwarthen/RomWBW/blob/master/Source/HBIOS/ppide.asm) than what you've used on your board. Contemplating if an RC2014 PIO interface was to be made, which would be the best mapping to pick. I'd be tempted to go with the RomWBW PPIDE mappings as there are already 2 boards using that format, and could run RomWBW without changes(unless your mapping is better :))?
I'm not sure if there is a PIO8255 IDE interface underway for the RC2014 but, if not, it would be a good time to start one.
If the hardware looks like this example, or on page 6 of attached schematic PDF, then the diskio layer already works.