About the equation based timing delay model

[wenchen]

Hi RapidWright

I have read the paper "An Open-source Lightweight Timing Model for RapidWright". I think this timing model is very useful, and I want to study it in detail, but I did not understand some part of the paper.

1. 

"delay(TG) = k0 + k1⋅L(TG) + k2⋅d(TG), where L(TG) represents the length of the wire segments, and d(TG) captures the additional distance a wire travels beyond a CLE column in the architecture. L(TG) is defined for each TG, but d(TG) is sum of d for all the tiles that TG passes through."

Is the net between two PIPs considered as a wire segement? And the length of the wire segments is the number of PIPs that this wire traverses?

What is a CLE column?

2. Could you please provide an example for global TG and a bounce TG? 

3. Could you please provide an example for calculating a net delay according to your equation?

Taking the highlighted net in the above figure, according to my ndividual  understanding, there are 4 horizontal wire segment, 2 vertical wire segment, and traverse 2BRAM and 1 DSP. 

delayh(TG) = k0h + k1h*L(TG)h+k2h*d(TG)h = 43+3.5*4+2.3*(2*16+1*3) = 137.5

delayv(TG) = k0v+ k1v*L(TG)v+k2h*d(TG)h = 43+3.6*2+0 = 50.2

The total delay is 187.7ps, which is far from the reported result 549ps. 

I know my understanding must be wrong, but I don’t know where it is wrong.

Merry Christmas!

Wen Chen 

 

[pongstorn.maidee]

Wen Chen

1) Not all nodes (you call it net in your question). Some nodes are local to an interconnect tile. Please refer to slide 8 of the attached pdf.  (it was presented at FPT 19)  A CLE tile is where SLICE is. In your picture, where you place V1 is an example of a CLE tile. A CLE column is a column of CLE tiles.  From your picture, h1 or h2 is not a segment or TG.  TG is defined between interconnect tiles. h1 and h2 are used to connect from BRAM to an interconnect tile.   Their delay will be part of BRAM because there are not common among other types of tiles, ie., CLE.

2) Bounce are nodes that allow jumping from a node connected to an input site pin to another input site pin. There are used to improve routability. Bounce TG will contain 2 nodes, the second node will have cost code name NODE_PINBOUNCE as shown in the picture below. Bounce nodes can have *BOUNCE* or *BYPASS* in  their name.  Global TG has only one node whose name contain GLOBAL. You can list them using   set b [get_nodes -of $t -filter {NAME=~INT_X24Y140/*GLOBAL*}]

3) please see slide 11 of the attach pdf. 

Best,

Pongstorn

[pongstorn.maidee]

Somehow, the picture for 2nd question was not shown above.

[pongstorn.maidee]

[wenchen]

Hi Pongstorn

Thank you for your patient reply!

But I still have some questions about your slides. 

1. Why the output site pin TG includes a PIP but the input site pin TG includes a whole interconnect tile?

2. Why the white-circled nodes are not calculated in the delay but the yellow-circled node is take into account?

3. Why the output site pin delay is not calculated but the input site pin delay is calculated?

Thank you again for your reply, happy new year!

Best regards,

Wen Chen

[pongstorn.maidee]

Hi Wenchen,

Sorry for late reply,

Somehow I don't see the picture here.

1) That picture is not meant to indicate what each TG include.   In general, output side pin TG contain only one node, while that of input site pin contain pip,none,pip,node.

2) An interconnect tiles have a single from the left to the right sides (and vice versa). The one with your yellow circle happen to be one of those. The route under your white circle does not contain such a single. These notation differs from what you usually seen in academic routing resource.

3) An output site pin has one to one connection to a site pin and the corresponding TG has only one node. Thus its delay is a part of logic delay.  In contrast, there are multiple way to get to an input site pin. Each of them is represented with different TGs. Thus, they might have different delays.

Best,

Pongstorn