TileColumnPattern and drawing Pblocks

[Syed Ahmed]

Hi,

I'm trying to draw Partial Reconfiguration Programmable Units (CLB PU, DSP PU, BRAM PU etc.) pblocks and using TileColumnPattern from RapidWright. As an example, when I used a {CLEM, CLEL_R} pattern, I get the following on vu9p. From the diagram, you can see that the last column that gets highlighted is 568, however there is a valid pattern of {CLEM, CLEL_R} at the next clock region (at 591 column). I have checked that the column is regular and there is no break in the pattern. Hence, I was wondering why didn't I get this column in the pattern map. Also, I was wondering how the TileColumnPattern is generated. Is there a tcl script that generates it? Since I'm trying to build a database of valid pblocks for a device, I'm trying to generalize it over multiple devices. Thanks in advance!

Best,

Syed Ahmed

PhD Student, UPenn

[Syed Ahmed]

Answering my questions,

- the column 591 doesn't get highlighted because it's a different CLB PU pattern that my program didn't account for (CLEM_R, CLEL_R)

- TieColumnPattern is generated inside RapidWright (confirmed with Chris at FPGA 2020).