Question from Xilinx Community Forums: Using DREAMPlace with RapidWright

[RapidWright]

A comment from the Xilinx Community Forums:

RapidWright is a very exciting development and I have been thinking about how to add a tool in the red "secret sauce" area. What I am considering is not so secret but a new placer which uses ML for placement as described here: https://github.com/limbo018/DREAMPlace. Would it be possible to do FPGA placement with DREAMPlace and use the Xilinx placer as refinement tool? The speed of DREAMPlace for ASIC flows seems incredible and it would really help with FPGAs too.

Any comments, suggestions would be welcome.

 

-Kal

[RapidWright]

Hi Kal,

It is possible that the approach in DREAMPlace could be adapted to Xilinx FPGAs by using RapidWright as the architectural fabric and legalization step.  This is precisely one of the reasons why we have created RapidWright to enable and foster innovation in the implementation stage of FPGA compilation.  We are currently interested in building out placement and routing capabilities for RapidWright and thank you for your suggestion.  

I'm not sure about exactly how DREAMPlace works in terms of legalization and its grasp of design rules, but if its able to reason about how different components should be placed together spatially, it seems like it would certainly be of use in FPGA placement problems.  First step might be to identify how it reasons about ASIC area and how that could be adapted such that it could reason about FPGA fabric.  Definitely an interesting project.

- Chris