Hi Chris,
I'm trying to understand the basic concept of RapidWright, but I cannot figure out the difference between EDIFCell and EDIFCellInst. As given in the RapidWright tutorial, EDIF package are related to logical netlist. As far as I can understand, EDIFCell is used to store a logical netlist component that can be LUT, FDRE, IBUF, OBUF and so on. EDIFCellInst is the instance in the design.
To better illustrate my problems, I provide a simple example.
module top(
input clk,
input [1:0] in0,
input [1:0] in1,
output [3:0] out);
reg [2:0] result;
always @(posedge clk)
result <= {(in1[1]&in0[1])|((in1[0]&in0[0])&(in1[1]^in0[1])),(in1[1]^in0[1])^(in1[0]&in0[0]),in1[0]^in0[0]};
assign out[2:0] = result;
assign out[3] = in1[1];
endmodule
If my understanding is right, in the above schmetic,
1. LUT2, LUT4, IBUF, OBUF, FDRE... are EDIFCell, while result[0]_i_1, result[1]_i_1, result[2]_i_1, result_reg[0], result_reg[1]... are EDIFCellInsts.
2. The EDIFLibrary contains LUT2, LUT4, IBUF, OBUF, FDRE rather than result[0]_i_1, result[1]_i_1, result[2]_i_1, result_reg[0], result_reg[1].
3. LUT4.getCellInsts() will be result[1]_i_1, result[2]_i_1
4. result[1]_i_1.getCell() will be LUT4
Then I synthesis (only synthesis, no P&R) the verilog code in Vivado and load the dcp into RapidWright.
Design design = Design.readCheckpoint(args[0]);
EDIFNetlist netlist = design.getNetlist();
EDIFLibrary library = netlist.getLibrary("hdi_primitives");
for(EDIFCell Cell : library.getCells()){
for(EDIFCellInst CellInst : Cell.getCellInsts()){
System.out.println(Cell.getName()+'/'+CellInst.getName());
}
}
My expected output is:
GND
VCC
BUFGCE/clk_IBUF_BUFG_inst
OBUF/out_OBUF[0]_inst
OBUF/out_OBUF[1]_inst
...
LUT2/result[1]_i_0
...
IBUF
However, the actual output is
IBUF/IBUFCTRL_INST
IBUF/INBUF_INST
There must be something wrong with my understanding, but where is it?
Thank you
Wen Chen