module top( input clk, input [1:0] in0, input [1:0] in1, output [3:0] out); reg [2:0] result;
always @(posedge clk) result <= {(in1[1]&in0[1])|((in1[0]&in0[0])&(in1[1]^in0[1])),(in1[1]^in0[1])^(in1[0]&in0[0]),in1[0]^in0[0]}; assign out[2:0] = result; assign out[3] = in1[1];
endmodule
design = Design.readCheckpoint('top.dcp')netlist = design.getNetlist()library = netlist.getLibrary("hdi_primitives")topCell = netlist.getTopCell()
...
design.placeIOB(topCell.getCellInst("clk_IBUF_inst"), "E3", "LVCMOS33")
def placeCells(design): cell_names = design.getNetlist().getTopCell().getCellInsts().toArray().tolist() placement_list = [] for cell_name in cell_names: print(str(cell_name.getCellType())+'/'+str(cell_name)) if ("BUFG" in str(cell_name.getCellType())): cell = design.createCell(str(cell_name),cell_name) site = design.getDevice().getSite("BUFGCTRL_X0Y16") bel = site.getBEL("BUFG") design.placeCell(cell,site,bel) print(bel)
placeCells(design)
GND/GNDVCC/VCCBUFG/clk_IBUF_BUFG_inst...ERROR: Site type BUFGCTRL not supported for cell type BUFG
elif ("BUFG" in str(cn.getCellType())): cell = design.createCell("BUFGCTRL", Unisim.BUFGCTRL)
site = design.getDevice().getSite("BUFGCTRL_X0Y16")
bel = site.getBEL("BUFGCTRL") design.placeCell(cell,site,bel)