Synopsys Ic Compiler Ii

[Brian]

MOUNTAINVIEW, Calif., Feb. 7, 2014 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced it has completed the acquisition of Target Compiler Technologies, a privately held company headquartered in Leuven, Belgium, that provides software tools to design and program application-specific instruction-set processors (ASIPs). ASIPs complement industry-standard processor architectures by enabling designers to implement their own highly specialized software programmable engines for compute-intensive digital signal and data plane processing. The acquisition of Target strengthens Synopsys' existing ASIP tools portfolio while bringing a world-class team of ASIP experts into the company.

"As today's SoCs rely more on heterogeneous multi-core architectures, designers are turning to ASIPs to implement their unique data plane and digital signal processing requirements," said John Koeter, vice president of marketing of IP and Systems at Synopsys. "Target's leading IP Designer and MP Designer software tools perfectly complement Synopsys' offerings for ASIP developers, enabling design teams to develop ASIPs that meet their performance, power, and flexibility requirements more efficiently and with less risk."

Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.

I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial tools, but I'm working my way into SiliconCompiler (Yosys, OpenROAD, etc.).

Memory compilers are needed because the physical structure of memories go beyond the Boolean logic most synthesis tools are designed to work with. They are also very dependent on the target ASIC technology used to implement them, usually in CMOS primitives instead of logic gates.

And since they are very large, regular structures, they can be generated by simple replication rather than feeding massive sets of logic equations to a synthesis tool. That gives you better results (area/timing) versus what can be achieved with pure logic equations.

Use "ls" commend to check if "library.lib" is in your synopsys directory. This file contains logical descriptions and timing information for a set of logic gates (cells).The first time you use Synopsys, you probably won't have a cell library yet, so you should use this library as-is. The library file contains definitions for an inverter, nand2, nand3, nand4, nor2, nor3, aoi12, aoi22, oai12, oai22, and d-flip-flop.When you create a cell library in Cadence later on, you will need to modify the Synopsys library file to match your cells.If your cells differ from those in the library file, you may need to change cell names, pin names, and /or logical descriptions in the library file to match; this shouldn't be much of a problem if you pay attention to the Synopsys library file when laying out your cells in Cadence.Timing information is a more advanced subject, so you shouldn't change the given values, although you may want to experiment with changing the reported delays to match those of your cells if time allows.

Synopsys' Physical Compiler Enables Tape Out of Enterprise Server ASIC

MOUNTAIN VIEW, Calif.----Oct. 16, 2000--Synopsys, Inc. (Nasdaq:SNPS), today announced that Unisys Corporation has successfully used Physical Compiler, Synopsys' Physical Synthesis tool, to tape out a high-performance, 200 MHz, 1.5 million gate, 0.18 micron ASIC. Physical Compiler has now been adopted as a standard part of the Unisys ASIC design flow. Before adopting Physical Compiler, the conventional Unisys back-end flow required intensive designer intervention resulting in design schedule unpredictability. Physical Compiler's unified synthesis and placement capability allowed Unisys to fix the last 1,000 timing violations in less than a week -- saving weeks of typical iterations. ``Timing closure is a significant challenge,'' said Wayne Engstrom, engineering director, Unisys Systems and Technology. ``With Physical Compiler, we saved several weeks of manual iteration on a very complex design. We have successfully inserted Synopsys' Physical Compiler into our standard ASIC design process, which includes Synopsys' Design Compiler and our ASIC vendor-supplied back-end tools.'' ``We are extremely pleased at the success Unisys has achieved with Physical Compiler on one of their toughest designs,'' said Sanjiv Kaul, senior vice president and general manager for Synopsys' Physical Synthesis business unit. ``Tape outs are the true measure of success for an implementation tool. This tape out builds upon the success that Synopsys' Physical Synthesis has demonstrated through more than 25 tape outs of networking, communications, computing, and graphics chips.'' Synopsys' Physical Synthesis Solution Pioneered by Synopsys, Physical Synthesis helps designers address the implementation challenges of next-generation system-on-chip designs. Physical Synthesis brings key physical design considerations to the front-end, allowing RTL designers to rapidly achieve high quality of results. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Synopsys' Physical Synthesis leverages industry-standard tools such as Design Compiler(TM), Module Compiler(TM) and PrimeTime and its proven interfaces to third-party solutions allow it to easily plug into an existing design flow. Pricing and Availability Physical Compiler is available now. Pricing for a single-user, one-year term license begins at $100,000. Support and maintenance options vary and are in addition to the product license. About Unisys Unisys is an e-business solutions company whose 36,000 employees help customers in 100 countries apply information technology to seize opportunities and overcome challenges of the Internet economy. Unisys people integrate and deliver the solutions, services, platforms and network infrastructure required by business and government to transform their organizations for success in this new era. The company offers a rich portfolio of Unisys e-@ction Solutions for e-business based on its expertise in vertical industry solutions, network services, outsourcing, systems integration and multivendor support, coupled with enterprise-class server and related technologies. The primary vertical markets Unisys serves worldwide include financial services, transportation, communications, publishing and commercial sectors, as well as the public sector, including federal government customers. Unisys is headquartered in Blue Bell, Pennsylvania, in the Greater Philadelphia area. For more information on the company, access the Unisys home page on the World Wide Web at About Synopsys Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Design Compiler and Module Compiler are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. Contact: Synopsys, Inc. Robert Smith, 650/584-1261 rsm...@synopsys.com or KVO Public Relations Bill Warner, 503/402-1449 bill_...@kvo.com

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Estimation of power consumption of an integrated circuit at RT level can be handy since it allows designers to obtain an approximate and yet accurate enough estimate on total power consumption of their design in a very short time.

Basically, the designer runs the logic simulation for his pure RTL design and obtains the switching activity statistics for his circuit. The test bench developed by the designer for the logic simulation is indeed the workload imposed to the circuit and power will be estimated for this specific workload.

In this writing I go through the details of how power estimation at RT level can be done using the Synopsys Design Compiler environment. During my descriptions I suppose that Synopsys VCS is used for logic simulation.

And we have developed a test bench, in which we have instantiated the AXI_OpenRISC_top unit and we have also created the required logic to stress this unit. Suppose that the name of the test bench module is : AXI_OpenRISC_testbench

Then we have a Makefile, which uses the Synopsys VCS, compiles the design, performs the simulation and then uses the generated VCD files to prepare the main circuit switching activity statistics. Here is a simplified Makefile:

As you can see the Makefile introduces two targets: simv and saif. The simv target compiles the RTL and builds the main simulation executable file. Then the saif target first performs the logic simulation by running simv executable. The output of logic simulation is stored in a vpd file. The vcd2saif then reads the vpd file, and calculates the averaged switching activity for each element in the RTL. The generated saif file will then be given to the synthesis tool (Design Compiler) for estimating power at RTL.

To perform accurate RT level power estimation, you run the dc_shell in topographical mode (with -topo). Furthermore you inform the synthesis tool at the time of synthesis that later you want to perform RTL power estimation by using the switching activity statistics obtained from pure RTL simulation.

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