Rick,
Nice you are experimenting with the new pi-5 setup.
In the study document i mentioned:
I even did change the number of RX slices to 6 for the CL025 FPGA!
Making it possible to run for instance 6 channels @48K for doing wspr on 6 channels. By removing the
TX chain even more RX channels are achievable.(small change required in the firmware NR=4 to
NR=6; but better is to get this from the gateware)
This is still at the backlog.
Some remarks:
- I think when you only want to listenen you are able to set the TX at 0 and is should be able to have 7 RX channels running (NR=7)
- i have set the PIO speed by experimenting... no possiblity to measure.... still thinking of using an other pi-5 and make a logic analyser using the 200Mhz clock must be possible to measure!
- Using the clock at maximum should be possible but than you need to add some additonal delays in the statemachine.. as said defined by experiment...
Maybe you are able to measure?
In the driver:
config_args.config.clkdiv = 0x00020000; => 00010000 for no division; so use 200Mhz
config_args.config.execctrl = 0x5901f680;
config_args.config.shiftctrl = 0x00000000;
config_args.config.pinctrl = 0x40091800;
const uint16_t rx_iq_sample_program_instructions[] = {
0x80a0, // 0: pull block
0xa047, // 1: mov y, osr
0xa022, // 2: mov x, y
// .wrap_target
0x0013, // 3: jmp 19
0xbb42, // 4: nop side 1 [3]
0x5004, // 5: in pins, 4 side 0
0xbb42, // 6: nop side 1 [3]
0x5004, // 7: in pins, 4 side 0
0xbb42, // 8: nop side 1 [3]
0x5004, // 9: in pins, 4 side 0
0xbb42, // 10: nop side 1 [3]
0x5004, // 11: in pins, 4 side 0
0xbb42, // 12: nop side 1 [3]
0x5004, // 13: in pins, 4 side 0
0xbb42, // 14: nop side 1 [3]
0x5004, // 15: in pins, 4 side 0
0x8020, // 16: push block
0x0044, // 17: jmp x--, 4
0xa022, // 18: mov x, y
0xba42, // 19: nop side 1 [2]
0xb242, // 20: nop side 0 [2]
0x00c4, // 21: jmp pin, 4
// .wrap
};
this is the PIO:
.program rx_iq_sample
.side_set 1 opt ; 1-bit side-set (clock), optional
; sideset_base = 6
; data ready pin = GPIO 25
; data pins = in_base = {18, 19, 20, 21}
pull block
mov y, osr
mov x, y
.wrap_target
jmp poll_ready
read_sample:
; read 6 × 4 bits = 24 bits ; I or Q sample
nop side 1 [3]
in pins, 4 side 0 [0]
nop side 1 [3]
in pins, 4 side 0 [0]
nop side 1 [3]
in pins, 4 side 0 [0]
nop side 1 [3]
in pins, 4 side 0 [0]
nop side 1 [3]
in pins, 4 side 0 [0]
nop side 1 [3]
in pins, 4 side 0 [0]
push block
jmp x-- read_sample
mov x, y
poll_ready:
nop side 1 [2]
nop side 0 [2]
jmp pin read_sample
.wrap
Hope this gives some input for further experiments!
73 Johan
PA3GSB