Jose,
First iam not involved in the new design and new pcb layout; i am not making any money.
Looking through old messages:
The gateware version is collected via SPI commands.
There are mainly 2 reasons why you are getting these 0.0 or 255.255 as gateware version
- the gateware is not loaded (check the logging if the driver is loading the gateware)
- you are missing the ad9866 clock at pin 53.
The SPI interface is initialized (HDL fragment from gateware: spi_slave spi_slave_inst(.rstb(!reset)......)
The clock controls the reset flag... and so the initialization of the SPI interface in the gateware.
In /var/log/syslog you can check if the gateware is loaded.
I assume the clock is not present on pin 53/60 at the FPGA
Hope you are able to find the issue.
73 Johan
PA3GSB