This is a very nice setup. I am impressed that you can fit 8 4kHz receivers in a single FPGA. I could only fit 5, maybe due to the added overheads of ethernet on the HL2. Did you have to make any changes to fit 8?
Also, did you increase the decode depth to 3 in ft8d? In case you haven't done this, all you need to do is change ndepth to 3 in ft8d.f90 and rebuild. Pavel kept the decode depth at 1 so that it could run on the embedded A9 ARM in the Zynq, but I think the RPi should be able to handle 3. I did see more spots when increasing the depth to 3.