clk1 and clk 2

[Alex a]

Hi,

I have two questions.

1) How can we declare tow clock (clk1 and clk2) with different period in PyMTL3 ?

2) The concat operator works fine, when I use it after ‘@=’ ( s.a @= concat( s.b , s,c)). But when I use it before ‘@=’ ( concat(s.b, s.c) @= s.a), I get errors. So, is there an alternative idea to use the concatenation in this case ?

Thanks!

Best regards,

Alex

[Peitian Pan]

Hi Alex,

Thank you for using PyMTL3!

1) PyMTL3 currently does not support more than one clock domains. The primitives that allow you to model states will implicitly generate a clock of name `clk` if you translate your stateful components into Verilog or generate waveforms.

2) You are right that `concat` will not work on the left hand side (LHS) of a signal assignment. I like to think of `@=` as a _signal-assignment_ operator -- you are free to choose your RHS but the LHS has to be some signal. So you probably need to reorganize your code (e.g., assign s.b and s.c to some slices of s.a) because I don't think there's a super effective alternative to what you want...

Best,

Peitian

[Alex a]

Hi Peitian,

thanks for your reply.

I have another question.

How to initialize a wire with a constant in PyMTL3?

wire [4:0] a = 5'b01100;

 

 

Thanks!

Best regards,

Alex

[Christopher Batten]

Hi Alex,

There are two ways to assign constant to a signal. First you can use the connect operator (//=) to directly connect a signal to a constant in a single line like this:

s.a //= 0

Second, you can use a combinational update block with a blocking assignment like this:

@update
def upA():
s.a @= 0

Hope this helps!
Chris

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[Alex a]

Hi Chris,

thanks for your reply.

I get errors, when I write

s.a =Wire(3)

s.a //= 1

@update_ff

def block1():

     s.a <<=s.a+1

 

Is it possible to initialize (not assign) a wire with a constant in PyMTL3?

In other words, how to write the following line with PyMTL3?

 wire [4:0] a = 5'b01100;

 

Best regards,

Alex

[Christopher Batten]

Hi Alex,

Hmmm ... the code you wrote does not model real hardware. The equivalent in Verilog would be:

reg [2:0] a = 1;
always @( posedge clk ) begin
a <= a + 1;
end

If our try to synthesize this using an ASIC logic synthesis tool it will complain since it is not clear what hardware we are trying to model here. If you use an FPGA logic synthesis tool sometimes they will infer a reset flip-flop ...

I think what you want to do is reset the value of a counter to one? In which case in Verilog you would write:

reg [4:0] a;
always @( posedge clk ) begin
if (reset)
a <= 1;
else
a <= a + 1;
end

The above works fine in both an ASIC and FPGA logic synthesis tool. So in PyMTL3 you would basically do the same thing:

s.a = Wire(3)

@update_ff
def block1():
if reset:
s.a <<= 1
else:
s.a <<= s.a + 1
end

In PyMTL3 a reset and clk signal is inferred for all components ... and when you call sim_reset() on your top-level model it sets reset high for a few cycles and then sets it low ...

Hope this helps!
-c

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