An error occurred when converting a RTL Module into Verilog.

[Victor P]

I tried to run the code below:

from ChecksumRTL import ChecksumRTL

from pymtl3.passes.backends.yosys import YosysTranslationPass

cksum = ChecksumRTL()

cksum.set_metadata(YosysTranslationPass.enable, True)

cksum.elaborate()

cksum.apply(YosysTranslationPass())

success = True

Which is trying to compile the RTL Checksum Module (Example 2) into yosys-compatible SystemVerilog.

This piece of code is  extracted from "cksum-translate" file.

The error:

What could be wrong?

Thanks.

[Shunning Jiang]

Hi Victor,

I doubt this is a python version issue. Which Python version are you using? Starting from either Python3.6 or 3.7 virtual environment seems to work fine for me. We haven't tested pymtl3 under python3.8 yet.

Shunning

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Shunning Jiang

Ph.D. Candidate 

Computer Systems Laboratory

School of Electrical and Computer Engineering

Cornell University

http://www.csl.cornell.edu/~shunning

[Victor P]

Hi Shunning,

I am using Python 3.8.5.

Victor

[Shunning Jiang]

Can you try if Python 3.7 will work as a workaround for now? We will put the compatibility issue on our list.

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[Victor P]

Hi Shunning,

You were right, it was the problem caused by Python 3.8

Victor

On Sunday, September 13, 2020 at 12:16:17 AM UTC+8 Shunning Jiang wrote: