Question about apply YosysTranslationPass()

[Jiangqiu Shen]

My code passed the DefaultGroupPass, and when I try to translate it into verilog file, I got this error message

File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/backends/generic/RTLIRTranslator.py", line 28, in clear
    super().clear( tr_top )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/backends/generic/behavioral/BehavioralTranslatorL5.py", line 23, in clear
    super().clear( tr_top )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/backends/generic/behavioral/BehavioralTranslatorL1.py", line 26, in clear
    s.gen_behavioral_trans_metadata( tr_top )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/backends/generic/behavioral/BehavioralTranslatorL2.py", line 29, in gen_behavioral_trans_metadata
    super().gen_behavioral_trans_metadata( tr_top )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/backends/generic/behavioral/BehavioralTranslatorL1.py", line 40, in gen_behavioral_trans_metadata
    s._gen_behavioral_trans_metadata( tr_top )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/backends/generic/behavioral/BehavioralTranslatorL5.py", line 32, in _gen_behavioral_trans_metadata
    m.apply( BehavioralRTLIRTypeCheckL5Pass( s.tr_top ) )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/dsl/Component.py", line 530, in apply
    pass_instance( s )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL2Pass.py", line 61, in __call__
    type_checker.enter(blk, rtlir_upblks[blk])
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL1Pass.py", line 142, in enter
    s.visit( rtlir )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL1Pass.py", line 175, in visit
    s.visit( item )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL1Pass.py", line 171, in visit
    s.visit( value )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL1Pass.py", line 171, in visit
    s.visit( value )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL1Pass.py", line 198, in visit
    func( node )
  File "/home/sjq/.conda/envs/pymtl3/lib/python3.6/site-packages/pymtl3/passes/rtlir/behavioral/BehavioralRTLIRTypeCheckL2Pass.py", line 386, in visit_Compare
    l_type = node.left.Type.get_dtype()
AttributeError: 'Component' object has no attribute 'get_dtype

My generation code is like this:

 macc = Sized_memory_sender_in_order(
 Bits32, Bits64, 32, 1, 8)
 macc.set_metadata(YosysTranslationPass.enable, True)
 macc.elaborate()
 macc.apply(YosysTranslationPass())
 done = True

 and the component code is like this

class Sized_memory_sender_in_order(Component):
 def construct(s, size_type, addr_type, item_size, mem_request_dest, recv_queue_size):

 # types

 s.size_recv = RecvIfcRTL(size_type)
 s.addr_recv = RecvIfcRTL(addr_type)
 s.data_out = SendIfcRTL(mk_bits(item_size))
 s.mem_out = SendIfcRTL(Bits153)
 s.mem_in = RecvIfcRTL(Bits81)
 # buffers
 s.size_reg = RegEnRst(size_type)
 s.addr_reg = RegEnRst(addr_type)
 s.remaining_recv_reg = Reg(size_type)
 s.need_to_push_zero = Reg(Bits1)
 s.recv_queue = PipeQueueRTL(mk_bits(item_size), recv_queue_size)
 # logic
 s.size_en_mux = Mux(Bits1, 2)
 s.size_data_mux = Mux(size_type, 2)
 s.addr_en_mux = Mux(Bits1, 2)
 s.addr_data_mux = Mux(addr_type, 2)
 s.remaining_mux = Mux(size_type, 2)
 # connections

 # controled by mux
 s.remaining_recv_reg.in_ //= s.remaining_mux.out
 s.size_reg.en //= s.size_en_mux.out
 s.size_reg.in_ //= s.size_data_mux.out
 s.addr_reg.en //= s.addr_en_mux.out
 s.addr_reg.in_ //= s.addr_data_mux.out

 s.recv_queue.deq.ret //= s.data_out.msg
 # controled by outter signal

 s.addr_en_mux.in_[0] //= s.addr_recv.en
 s.addr_data_mux.in_[0] //= s.addr_recv.msg
 s.size_en_mux.in_[0] //= s.size_recv.en
 s.size_data_mux.in_[0] //= s.size_recv.msg
 s.remaining_mux.in_[0] //= s.size_recv.msg
 s.recv_queue.enq.rdy //= s.mem_in.rdy
 s.recv_queue.enq.en //= s.mem_in.en

 #s.recv_queue.enq.msg //= s.mem_in.msg[17:81]

 @update
 def comb():

 if s.need_to_push_zero.out == Bits1(0):
 s.recv_queue.enq.msg @= s.mem_in.msg[17:17+32]
 else:
 s.recv_queue.enq.msg @= Bits32(0)
 if s.need_to_push_zero.out & s.recv_queue.enq.rdy: # current need, and push it
 s.need_to_push_zero.in_ @=0
 elif s.remaining_recv_reg.out != size_type(0): # not need yet
 s.need_to_push_zero.in_ @=0
 else: # it's zero, push zero is needed
 s.need_to_push_zero.in_@=1
 s.recv_queue.deq.en @= s.recv_queue.deq.rdy & s.data_out.rdy
 s.data_out.en @= s.recv_queue.deq.rdy & s.data_out.rdy

 s.size_recv.rdy @=(s.size_reg.out != Bits32(
 0)) & (s.remaining_recv_reg.out == Bits32(0)) & (s.need_to_push_zero == Bits1(0))
 s.addr_recv.rdy @= (s.size_reg.out != Bits32(
 0)) & (s.remaining_recv_reg.out == Bits32(0)) & (s.need_to_push_zero == Bits1(0))

 # if the size is zero, listen to outsize sigal, else listen to my self
 s.size_en_mux.sel @= 0 if s.size_reg.out == size_type(0) else 1
 s.size_data_mux.sel @=0 if s.size_reg.out == size_type(0) else 1
 s.remaining_mux.sel @=0 if s.size_reg.out == size_type(0) else 1
 # build the request.

 s.mem_out.msg @= concat(Bits4(0),
 Bits8(mem_request_dest), s.addr_reg.out, Bits77(0))
 s.size_data_mux.in_[1] @= s.size_data_mux.out - 1
 # addr will change every round
 s.addr_data_mux.in_[
 1]@=s.addr_reg.out + item_size # addr offset

 s.size_en_mux.in_[
 1] @= s.mem_out.rdy & (s.size_reg.out != Bits32(0))
 s.mem_out.en @=s.mem_out.rdy & (s.size_reg.out != Bits32(0))
 s.addr_en_mux.in_[1]@=s.mem_out.rdy & (s.size_reg.out != Bits32(0))
 s.remaining_mux.in_[1]@=s.remaining_mux.out-1 if s.mem_out.rdy & (
 s.size_reg.out != Bits32(0)) else s.remaining_mux.out

can any one give me any suggestion?
 

[qiuqi...@gmail.com]

There's some formating error caused by copy-paste, like if and else indent, just ignore it.

[Shunning Jiang]

See the previous email. Also as a shorthand you can use b32 instead of Bits32. Now you can also directly write s.size_reg.out == 0 

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Shunning Jiang

Ph.D. Candidate 

Computer Systems Laboratory

School of Electrical and Computer Engineering

Cornell University

http://www.csl.cornell.edu/~shunning