Python verilog co-generation

[zhouwe...@gmail.com]

Hi,

      I'm a beginner of PyMTL, now thinking using PyMTL to generate a systolic array. To improve the hardware performance, I hope map some RTL level code on some primitives, e.g. map fixed-point multiply on DSP48e2, or write a processing element module in verilog first, and then PyMTL can call the verilog module for processing element and then generate a systolic array code. Is this idea supported on PyMTL now? Thank you!

[Christopher Batten]

Hi! Yes, PyMTL3 is perfect for developing accelerator generators. Checkout the OpenCGRA project from PNNL:

https://github.com/pnnl/OpenCGRA

This is an example of a CGRA generator written in PyMTL3.

I would recommend not writing the PE in verilog unless you absolutely have to. You can just write the PE in PyMTL3 to simplify design, verification, and simulation .. you can always translate your PyMTL3 RTL code into Verilog once you have a design you like ...

Best,
-c

> On Dec 18, 2020, at 6:50 AM, zhouwe...@gmail.com <zhouwe...@gmail.com> wrote:
>
> Hi,
> I'm a beginner of PyMTL, now thinking using PyMTL to generate a systolic array. To improve the hardware performance, I hope map some RTL level code on some primitives, e.g. map fixed-point multiply on DSP48e2, or write a processing element module in verilog first, and then PyMTL can call the verilog module for processing element and then generate a systolic array code. Is this idea supported on PyMTL now? Thank you!
>

> --
> You received this message because you are subscribed to the Google Groups "pymtl-users" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.
> To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/133d0838-5207-4cc8-a220-87430bc82d7dn%40googlegroups.com.