Finding Verilog Modules in Different Files

[Sebastian]

Hello,

Still dinking around with PyMTL and am baffled by a little ECE 5745 example.

I'm trying to test /my/path/regincr/RegIncrNstageVRTL.v (a 2-stage registered incrementer in my case) which has the line

`include "RegIncrVRTL.v"

So I also have the file /my/path/regincr/RegIncrVRTL.v

But whey I run my PyMTL code I get the error:

E   FileNotFoundError: [Errno 2] No such file or directory: '/my/path/regincr/regincr/RegIncrVRTL.v'

When I create the file /my/path/regincr/regincr/RegIncrVRTL.v, the problem goes away and the test executes fine.  

In fact, even when I entirely remove the `include line above from RegIncrVRTL.v, the test still executes fine (as long as /my/path/regincr/regincr/RegIncrVRTL.v is present of course).  

It **seems** like PyMTL has some way of finding the dependency, but only if the module is placed in an appropriately named subfolder.  Am I goofing somehow with my PyMTL code (examples below sign-off)?

Thanks, Sebastian

PyMTL Design Code (

from pymtl3 import *

from pymtl3.passes.backends.verilog import VerilogPlaceholderPass, VerilogPlaceholder
from os.path import dirname

class RegIncrNstageVRTL( Component, VerilogPlaceholder ):
def construct( s, nstages=2 ):
s.in_ = InPort ( Bits8 )
s.out = OutPort ( Bits8 )
s.set_metadata(VerilogPlaceholderPass.src_file, dirname(__file__) + '/RegIncrNstageVRTL.v')
s.set_metadata(VerilogPlaceholderPass.top_module, 'RegIncrNstageVRTL')
RegIncrNstageRTL = RegIncrNstageVRTL

PyMTL Test Code

from pymtl3.stdlib.test_utils import run_test_vector_sim, mk_test_case_table
from .RegIncrNstageRTL import RegIncrNstageRTL
def test_small( cmdline_opts ):
run_test_vector_sim( RegIncrNstageRTL(), [
('in_ out*'),
[ 0x00, '?' ],
[ 0x03, '?' ],
[ 0x06, '?' ],
[ 0x00, 0x05 ],
], cmdline_opts )

[Christopher Batten]

Hi Sebastian,

I think you really have to stay away from the ECE 5745 examples for now. We had to use a branch of PyMTL3 last year to have a stable version for teaching, but in the meantime in the spring we changed a bunch of things for the official PyMTL3 release. I will be updating all of the ECE 5745 materials this spring, but for now keep in mind that I don't think the ECE 5745 examples will work with the official PyMTL3 release ... sorry about that ... this is the struggle with developing a framework and trying to teach with it at the same time!

-c

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[Sebastian]

Thanks Christopher.  I'm happy to work from the public examples and plan to dive back to them soon, my one bind is that I would like to splice some hierarchically organized Verilog beside the PyMTL (I'm doing ASIC stuff, that has some blocks already done in that language).  But I'm afraid that's one thing I can't see in the available examples (i.e. public PyMTL interfaced to Verilog, maybe I missed some examples).  With Peitian's help it seems like a good chunk of the course stuff has been scrubbed out, alas just this issue (i.e. PyMTL -> Verilog -> Verilog -> ...).

Best, Sebastian

[Christopher Batten]

OK. I imagine Peitian can chime in. We have a very stylized way we write our Verilog to keep things organized and avoid namespace collisions, and I think by default our Verilog important assumes that things are organized in this way ... but I remember Peitian adding support for general Verilog import ... like you can specific include directories and stuff to Verilator ...

Any chance you can create a git repo or something with an example and we can take a look and see what needs to be fixed?

-c

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[Peitian Pan]

Hi Sebastian,

PyMTL3 performs regular expression matching through your Verilog code to capture lines of `include "filename" -- that FileNotFoundError was thrown because "filename" was not found in the current working directory.

I don't think PyMTL3 assumes any weird sub-directory names with the default settings. And I couldn't reproduce the same error you saw once I have the Python script (run_test.py) and the other two Verilog files in the same directory...

The error message also looks weird because it's looking at ".../regincr/regincr/..". Can you maybe make sure you have all three files (*.py and two *.v) under your current working directory and try again?

[Sebastian]

Hi Peitian,

I'm wondering if PyMTL's ability to parse the SV may not quite be discriminating enough at the moment.  

It **seems** to me like it has the ability to react to SV code that is commented out.  There was a bit of nuance to my code that I did not express above.  Specifically the code originally had the line `include "regincr/RegIncrVRTL.v"

I "removed" this by simply commenting it out (via //), I didn't actually delete the line.

But it seems that PyMTL was still processing this line and hence getting stuck when it could not find /regincr/regincr/RegIncrVRTL.v

It was not until I corrupted it, say // x`include "regincr/RegIncrVRTL.v", that it quit looking for  /regincr/regincr/RegIncrVRTL.v

Best, Sebastian

[Peitian Pan]

Re: parsing Verilog files. Right... currently PyMTL3 doesn't really _parse_ the Verilog file, but it simply matches a regular expression against that file which means it could misinterpret semantics of your file (like the error you pointed out in the comments).

[Christopher Batten]

But maybe our regular expression can filter out `includes which have been commented out? I know I have run into this before too?
-c

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[Peitian Pan]

Right... it is possible to check for comments first before searching for the regular expressions.