Testing Verilog in PyMTL3

[Sebastian]

Hello,

Just trying to run some pre-made SystemVerilog (SV) code (just the register incrementer) through PyMTL3.  But I am getting a 

TypeError: 'module' object is not callable 

coming back from my test code (just a very basic "test_small( cmdline_opts )" function) .  

The test code is part of exactly the same *_test.py file that works for a PyMTL3 implementation of the register incrementer so I must not be creating and/or linking correctly (among other things?).  My intuition is that I may not be "placing" and "translating" the SV correctly and I provide an example of my register incrementer code below the sign-off (mostly a copy of the example from ECE5745).  I'm hoping that that's enough to indicate what my error is.

Thanks again,

Sebastian

my 

class RegIncrVRTL( Component, Placeholder ):
  def construct( s ):
    s.in_ = InPort ( Bits8 )
    s.out = OutPort ( Bits8 )
    s.config_placeholder = VerilogPlaceholderConfigs(src_file='/my/path/regincr/RegIncrVRTL.v')
    s.config_verilog_translate = VerilogTranslationConfigs(explicit_module_name='RegIncrRTL')
    RegIncrRTL = RegIncrVRTL

a snippet of my test code is

def test_small( cmdline_opts ):run_test_vector_sim( RegIncrRTL(), [
('in_ out*'),

…

], cmdline_opts )

[Peitian Pan]

We have deprecated the use of magic attributes as a way to supply pass configurations. Instead PyMTL3 now has a metadata mechanism that allows you to set metadata related to some pass. For example: 

from pymtl3 import *

from pymtl3.stdlib.test_utils import run_test_vector_sim

from pymtl3.passes.backends.verilog import VerilogPlaceholderPass, VerilogPlaceholder

from os.path import dirname

class RegIncrVRTL( Component, VerilogPlaceholder ):

  def construct( s ):

    s.in_ = InPort( 8 )

    s.out = OutPort( 8 )

    s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/RegIncrVRTL.v' )

    s.set_metadata( VerilogPlaceholderPass.top_module, 'RegIncrVRTL' )

RegIncrRTL = RegIncrVRTL

def test_imported( cmdline_opts ):

  run_test_vector_sim( RegIncrRTL(), [

    ('in_ out*'),

    [0x00, '?'],

    [0x03, 0x01],

    [0x06, 0x04],

    [0x00, 0x07],

  ], cmdline_opts )

The snippet above demonstrates how to import an existing Verilog module `RegIncrVRTL` into PyMTL3. Note that we use the `set_metadata` API to specify the source Verilog file and module name as inputs to the VerilogPlaceholderPass.

Also we have renamed `Placeholder` to `VerilogPlaceholder` -- in the future PyMTL3 might support more backends (e.g., we might have `SystemCPlaceholder`)!

[Sebastian]

Thank-you Peitian I think it worked!

Best, Sebastian