Hi,
I used to program with verilog and I want to learn PyMTL3 so I want to know how to write the following red lines with PyMTL3
assign w_CARRY [0] = 1'b0;
assign o_result = {w_CARRY[2], w_SUM }; // Verilog Concatenation
`include "full_adder.v"
module ripple_carry_adder_2_FA
(
input [1:0] i_add_term1,
input [1:0] i_add_term2,
output [2:0] o_result
);
wire [2:0] w_CARRY;
wire [1:0] w_SUM;
// No carry input on first full adder
assign w_CARRY[0] = 1'b0;
full_adder full_adder_1
(
.i_bit1(i_add_term1[0]),
.i_bit2(i_add_term2[0]),
.i_carry(w_CARRY[0]),
.o_sum(w_SUM[0]),
.o_carry(w_CARRY[1])
);
full_adder full_adder_2
(
.i_bit1(i_add_term1[1]),
.i_bit2(i_add_term2[1]),
.i_carry(w_CARRY[1]),
.o_sum(w_SUM[1]),
.o_carry(w_CARRY[2])
);
assign o_result = {w_CARRY[2], w_SUM }; // Verilog Concatenation
endmodule
Thanks
Best regards,
Marcel
On May 23, 2021, at 2:48 PM, Peitian Pan <pp...@cornell.edu> wrote:
Hi Marcel,
To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/346077be-be44-45eb-b54e-c55102585e6dn%40googlegroups.com.
Best regards,
Marcel
To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/1bf0e2c1-21b1-4f9c-a4a1-51a9521125f3n%40googlegroups.com.