failure in run_sim

[David Peng]

Hi,

I encountered an error when executing run_sim:

=================================== FAILURES ===================================
__________________________________ test_basic __________________________________

    def test_basic():
      logging.basicConfig(level=logging.DEBUG)
      th = SchTH()
>     run_sim(th)

test/test_SchFL.py:13:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/stdlib/test_utils/test_helpers.py:223: in run_sim
    model = config_model_with_cmdline_opts( model, cmdline_opts, duts )
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/stdlib/test_utils/test_helpers.py:128: in config_model_with_cmdline_opts
    top.apply( VerilogPlaceholderPass() )
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/dsl/Component.py:530: in apply
    pass_instance( s )
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/passes/PlaceholderPass.py:50: in __call__
    s.__call__( child )
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/passes/PlaceholderPass.py:50: in __call__
    s.__call__( child )
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/passes/PlaceholderPass.py:49: in __call__
    for child in m.get_child_components(repr):
../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/dsl/Component.py:544: in get_child_components
    return s._collect_objects_local( lambda x: isinstance( x, Component ), sort_key )
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

s = <PortFL.PortFL object at 0x106ed4288>
filt = <function Component.get_child_components.<locals>.<lambda> at 0x1182f7318>
sort_key = <built-in function repr>

    def _collect_objects_local( s, filt, sort_key = None ):
>     assert s._dsl.constructed
E     assert False
E      +  where False = <pymtl3.dsl.NamedObject.DSLMetadata object at 0x1182871c8>.constructed
E      +    where <pymtl3.dsl.NamedObject.DSLMetadata object at 0x1182871c8> = <PortFL.PortFL object at 0x106ed4288>._dsl

../../.pyenv/versions/3.7.16/lib/python3.7/site-packages/pymtl3/dsl/Component.py:90: AssertionError
- generated xml file: /var/folders/c3/66fgmynn4ynfhlrp2dp09h6m0000gn/T/tmp-17439j6sLA4zAfKEO.xml -
=========================== short test summary info ============================
FAILED test/test_SchFL.py::test_basic - assert False
============================== 1 failed in 6.48s ===============================

any suggestion how to debug such issue?

Does pymtl3 need all classes under parent class as children of Components? I have mixed component's children and normal class. Below is my main DUT:

class SchDUT(Component):

def construct(s, inputs_, out):

s.ifg = 20

s.bus_width = 256

s.ing_fifo_nbytes = 10000

s.num = len(inputs_)

s.ing_ports = [None] * s.num

s.ing_bufs = [None] * s.num

for i in range(s.num):

s.ing_ports[i] = PortFL(inputs_[i], s.ing_bufs[i], s.bus_width, s.ifg)

s.ing_bufs[i] = FifoFL(s.ing_fifo_nbytes)

s.sch = RRFL(s.ing_bufs) # normal class

s.out_port = PortFL(s.sch, out, s.bus_width, s.ifg)

Thanks,

David

[Christopher Batten]

Hi David,

In general I don't think there is any issue with having members of a PyMTL component that do not inherit from the PyMTL3 Component base class. I just checked an example and this works fine ...

Can you maybe point us to some code in a Git repo and provide step-by-step instructions on how to reproduce your issue and we can take a look?

Best,

Chris

--
You received this message because you are subscribed to the Google Groups "pymtl-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/0f41bf5a-a3f0-4593-a127-b1de6ff8fc40n%40googlegroups.com.

[Peitian Pan]

Hi David,

I think there might be an issue in this part of your code:

s.ing_ports = [None] * s.num

s.ing_bufs = [None] * s.num

for i in range(s.num):

s.ing_ports[i] = PortFL(inputs_[i], s.ing_bufs[i], s.bus_width, s.ifg)

s.ing_bufs[i] = FifoFL(s.ing_fifo_nbytes)

Internally PyMTL3 replaces the attribute assignment operator of a Python class to allow inspections of the LHS and RHS or the assignment. Can you try replacing the above lines with the following (using list comprehension):

s.ing_ports = [ PortFL(inputs_[i], s.ing_bufs[i], s.bus_width, s.ifg ) for i in range(s.num) ]

s.ing_bufs = [ FifoFL(s.ing_fifo_nbytes) for i in range(s.num) ]

In general I think `s.array[i] = ...` style of assignment in the construction could lead to errors you saw... In cases like this definitely prefer list comprehension over mutation individual list elements.

Best,

Peitian

[Christopher Batten]

Good detective work Peitian! I just tried replacing this:

    s.reg_incrs = [ RegIncr() for _ in range(nstages) ]

with this:

    s.reg_incrs = [None]*nstages

    for i in range(nstages):

      s.reg_incrs[i] = RegIncr()

in our registered incremented example, and it doesn't work ... I think we have just gotten so use to list comprehensions I forgot this did not work!

Best,

Chris

-- 
You received this message because you are subscribed to the Google Groups "pymtl-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.

To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/e4bf5e83-75d3-4afa-89bf-6d71b6b35dffn%40googlegroups.com.

[David Peng]

Hi, Chris/Peitian,

Yes, this is exactly the error and fix. Great catch.

I know python list comprehension is powerful and elegant for some. But using for-loop as above is still quite common, for example, if I want to do more complicated configurable generation of different components. As a user I'll suggest you to still support this old-style by optimizing your checker. I am not the tool developer but I really can't see why my above code breaks your inspection.

Thanks,

David