Hello,
I am new to PyMTL and I'm interested in utilizing PyMTL3 or PyMTL3-net for my research.
To be more specific, my goal is to create a Verilog model of a single router using PyMTL3(-net), and later, evaluate the area and timing overhead using a synthesis tool.
While I've managed to modify the router design in PyMTL3-net, I found that synthesizing the entire network (such as mesh or ring) is unnecessary for my research; all I require is a model of a single router. Thus, I have two questions:
1. Is it possible to generate a Verilog model of a single router design using PyMTL3-net (or PyOCN)?
2. If this isn't possible, would it be more practical (or advisable) to create the router design using PyMTL3?
Thank you in advance!
from pymtl3.stdlib.test_utils import (run_sim,
config_model_with_cmdline_opts)
def test_translate( cmdline_opts ):
dut = MyRouter()
dut = config_model_with_cmdline_opts( dut, cmdline_opts, duts=[] )
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$ cd pymtl3_net/meshnet/test
$ mkdir build && cd build
$ pytest ../MeshRouteUnitRTLMflitXY_test.py --test-verilog -k test_1pkt
from pymtl3.stdlib.test_utils import (run_sim,
config_model_with_cmdline_opts)
def test_translate( cmdline_opts ):
dut = MyRouter()
dut = config_model_with_cmdline_opts( dut, cmdline_opts, duts=[] )
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