Weird Error When Doing Verilog Translations

[Victor P]

Hi here,

This is the code order that the Translation Passes works:

#Code----------------------------------------------------------------------------------

from pymtl3 import *

from pymtl3.passes.backends.verilog import *

class FlipFlopGL( Component ):

def construct( s ):

s.d = InPort()

s.q = OutPort()

@update_ff

def upblk():

s.q <<= s.d

dut = FlipFlopGL()

dut.set_metadata( VerilogTranslationPass.enable, True )

dut.apply( VerilogTranslationPass() )

dut.apply(DefaultPassGroup(textwave=True))

dut.sim_reset()

dut.d @= 1

dut.sim_tick()

dut.print_textwave()

#END-------------------------------------------------------------------------------------

When I put 

'dut.set_metadata( VerilogTranslationPass.enable, True )'

'dut.apply( VerilogTranslationPass() )'

to the end of Code (after 'dut.print_textwave()')

I got the error:

env:

Python Version: 3.7.9

Installed PyMTL3: the default version by pip3 install pymtl3

OS: Ubuntu 20.04

Is this an indented error? Thanks.

[Shunning Jiang]

Hi Victor,

It's because currently after applying the default pass group to enable simulation of the DUT, some of the metadata is destroyed. Basically applying verilog translation pass after applying simulation pass wouldn't work as of now. If you really need this feature, let us know and we will see what we can do.

Shunning

--
You received this message because you are subscribed to the Google Groups "pymtl-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/3ec40499-cd71-4dc4-958e-a11977e544ecn%40googlegroups.com.

--

Shunning Jiang

Ph.D. Candidate 

Computer Systems Laboratory

School of Electrical and Computer Engineering

Cornell University

http://www.csl.cornell.edu/~shunning