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This group is for questions, suggestions, and discussion within the PyMTL3 user community.
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King Lok Chung
11/27/23
Loop unrolling
Hi, Is it possible to make pymtl3 to unroll range loop and emit the Verilog instead of outputting a
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Loop unrolling
Hi, Is it possible to make pymtl3 to unroll range loop and emit the Verilog instead of outputting a
11/27/23
김지현
, …
Christopher Batten
8
8/23/23
Generate the single router design
Glad to hear it is working! -c On Aug 23, 2023, at 6:43 AM, Jihyun Kim <kimjh...@gmail.com>
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Generate the single router design
Glad to hear it is working! -c On Aug 23, 2023, at 6:43 AM, Jihyun Kim <kimjh...@gmail.com>
8/23/23
David Peng
,
Christopher Batten
4
5/20/23
cycle counter
Hi David, There is no support for this out of the box ... you could either write your own PyMTL3 pass
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cycle counter
Hi David, There is no support for this out of the box ... you could either write your own PyMTL3 pass
5/20/23
David Peng
,
Christopher Batten
2
5/19/23
decorator on update_once block
Hmmm … not sure if we have ever tried that. Sounds like you figured out a way to make it work though?
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decorator on update_once block
Hmmm … not sure if we have ever tried that. Sounds like you figured out a way to make it work though?
5/19/23
David Peng
, …
Christopher Batten
5
5/18/23
failure in run_sim
Hi, Chris/Peitian, Yes, this is exactly the error and fix. Great catch. I know python list
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failure in run_sim
Hi, Chris/Peitian, Yes, this is exactly the error and fix. Great catch. I know python list
5/18/23
Damian Rypel
,
Christopher Batten
4
5/5/23
Verilog verification in pymtl - general questions
Hi Damian, But you don't have any "classic" documentation eg with explanations what
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Verilog verification in pymtl - general questions
Hi Damian, But you don't have any "classic" documentation eg with explanations what
5/5/23
David Peng
, …
Christopher Batten
7
4/26/23
test-verilog FileNotFoundError
We will probably post on this list but you can of course still use PyMTL with the older version of
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test-verilog FileNotFoundError
We will probably post on this list but you can of course still use PyMTL with the older version of
4/26/23
David Peng
, …
Christopher Batten
14
4/22/23
weird error on @= assign to list of InPort
You could check out this paper: https://www.csl.cornell.edu/~cbatten/pdfs/jiang-mamba-dac2018.pdf If
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weird error on @= assign to list of InPort
You could check out this paper: https://www.csl.cornell.edu/~cbatten/pdfs/jiang-mamba-dac2018.pdf If
4/22/23
David Peng
,
Christopher Batten
2
4/19/23
pymtl3 still active supported?
Hi David, PyMTL3 is definitely still active although most of the users are all at Cornell currently.
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pymtl3 still active supported?
Hi David, PyMTL3 is definitely still active although most of the users are all at Cornell currently.
4/19/23
Sebastian
,
Christopher Batten
2
8/17/22
Multi "Line" Trace
I think you need to write your own tracing functions then? The line tracing is setup to output
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Multi "Line" Trace
I think you need to write your own tracing functions then? The line tracing is setup to output
8/17/22
Alex a
, …
Christopher Batten
6
7/10/21
clk1 and clk 2
Hi Alex, Hmmm ... the code you wrote does not model real hardware. The equivalent in Verilog would be
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clk1 and clk 2
Hi Alex, Hmmm ... the code you wrote does not model real hardware. The equivalent in Verilog would be
7/10/21
Marcel M
, …
Shunning Jiang
11
5/25/21
Concatenation + assign statement
I downloaded Python 3.7 and now it works fine . Thank you so much. Best regards, Marcel Le mardi 25
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Concatenation + assign statement
I downloaded Python 3.7 and now it works fine . Thank you so much. Best regards, Marcel Le mardi 25
5/25/21
Victor P
,
Peitian Pan
2
5/17/21
type object 'VcdGenerationPass' has no attribute 'vcdwave'
Hi Victor, Thanks for reaching out to us! We have identified this as an uncaught bug introduced in an
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type object 'VcdGenerationPass' has no attribute 'vcdwave'
Hi Victor, Thanks for reaching out to us! We have identified this as an uncaught bug introduced in an
5/17/21
Enze
, …
Shunning Jiang
3
4/18/21
Multiple Entry into @update_once block
Thanks for the report. I finally got a chance to fix it on master. On Fri, Feb 19, 2021 at 10:28 PM
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Multiple Entry into @update_once block
Thanks for the report. I finally got a chance to fix it on master. On Fri, Feb 19, 2021 at 10:28 PM
4/18/21
Victor P
,
Shunning Jiang
2
3/23/21
What changes have made to VerilatorImportConfigs and TranslationConfigs?
Hi, we have slightly revamped the way to do these pass configurations. You can take a look here https
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What changes have made to VerilatorImportConfigs and TranslationConfigs?
Hi, we have slightly revamped the way to do these pass configurations. You can take a look here https
3/23/21
Enze
,
Christopher Batten
5
2/21/21
Parallel "Threads" In PyMTL Testbench
Hi Enze, Right ... we usually use the "instantiate components to create test benches"
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Parallel "Threads" In PyMTL Testbench
Hi Enze, Right ... we usually use the "instantiate components to create test benches"
2/21/21
Enze
,
Christopher Batten
2
2/13/21
PyMTL Testbench Compatibility with VHDL
Hi Enze, Thanks for reaching out! Unfortunately, I don't think there is an easy path to
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PyMTL Testbench Compatibility with VHDL
Hi Enze, Thanks for reaching out! Unfortunately, I don't think there is an easy path to
2/13/21
zhouwe...@gmail.com
,
Christopher Batten
2
12/18/20
Python verilog co-generation
Hi! Yes, PyMTL3 is perfect for developing accelerator generators. Checkout the OpenCGRA project from
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Python verilog co-generation
Hi! Yes, PyMTL3 is perfect for developing accelerator generators. Checkout the OpenCGRA project from
12/18/20
Sebastian
,
Peitian Pan
2
11/21/20
Assert Error in AstHelper.py in python3.9 (Mac+Homebrew)
Please note that PyMTL3 currently does not officially support Python > 3.7. Since this assertion
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Assert Error in AstHelper.py in python3.9 (Mac+Homebrew)
Please note that PyMTL3 currently does not officially support Python > 3.7. Since this assertion
11/21/20
Sebastian
, …
Peitian Pan
9
11/20/20
Finding Verilog Modules in Different Files
Right... it is possible to check for comments first before searching for the regular expressions. On
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Finding Verilog Modules in Different Files
Right... it is possible to check for comments first before searching for the regular expressions. On
11/20/20
Sebastian
,
Peitian Pan
3
11/19/20
Testing Verilog in PyMTL3
Thank-you Peitian I think it worked! Best, Sebastian On Thursday, November 19, 2020 at 2:34:06 PM UTC
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Testing Verilog in PyMTL3
Thank-you Peitian I think it worked! Best, Sebastian On Thursday, November 19, 2020 at 2:34:06 PM UTC
11/19/20
Sebastian
,
Peitian Pan
4
11/18/20
VCD Dumps Possible in PyMTL3?
I have seen this before on an alpha version of PyMTL3 -- we saw really weird shared library issues
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VCD Dumps Possible in PyMTL3?
I have seen this before on an alpha version of PyMTL3 -- we saw really weird shared library issues
11/18/20
Sebastian
,
Christopher Batten
7
10/25/20
Very Basic: PyMTL3 problems with dump-vcd argument
It should work fine even without textwave=True though? That is just there to give you the cute little
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Very Basic: PyMTL3 problems with dump-vcd argument
It should work fine even without textwave=True though? That is just there to give you the cute little
10/25/20
Victor P
,
Shunning Jiang
2
10/23/20
Weird Error When Doing Verilog Translations
Hi Victor, It's because currently after applying the default pass group to enable simulation of
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Weird Error When Doing Verilog Translations
Hi Victor, It's because currently after applying the default pass group to enable simulation of
10/23/20
Victor P
,
Shunning Jiang
5
9/13/20
An error occurred when converting a RTL Module into Verilog.
Hi Shunning, You were right, it was the problem caused by Python 3.8 Victor On Sunday, September 13,
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An error occurred when converting a RTL Module into Verilog.
Hi Shunning, You were right, it was the problem caused by Python 3.8 Victor On Sunday, September 13,
9/13/20
qiuqi...@gmail.com
,
Christopher Batten
3
8/6/20
Get the Area and current latency
sure, thanks for your reply. On Thursday, August 6, 2020 at 9:03:24 AM UTC-4 silicon....@gmail.com
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Get the Area and current latency
sure, thanks for your reply. On Thursday, August 6, 2020 at 9:03:24 AM UTC-4 silicon....@gmail.com
8/6/20
qiuqi...@gmail.com
, …
Peitian Pan
13
8/5/20
About use mflow gen to get synthesis information
Hi Peitian, Thanks for your reply. After removing all the size casting, my code works! On Wednesday,
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About use mflow gen to get synthesis information
Hi Peitian, Thanks for your reply. After removing all the size casting, my code works! On Wednesday,
8/5/20
Shunning Jiang
,
qiuqi...@gmail.com
2
8/1/20
Re: [pymtl-users] Fail to translate the Component
Thank you very much! That workds, the correct code is: s.need_to_push_zero.out ==Bits1(0) On Saturday
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Re: [pymtl-users] Fail to translate the Component
Thank you very much! That workds, the correct code is: s.need_to_push_zero.out ==Bits1(0) On Saturday
8/1/20
Jiangqiu Shen
,
Shunning Jiang
3
8/1/20
Question about apply YosysTranslationPass()
See the previous email. Also as a shorthand you can use b32 instead of Bits32. Now you can also
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Question about apply YosysTranslationPass()
See the previous email. Also as a shorthand you can use b32 instead of Bits32. Now you can also
8/1/20
Taeyoung Kong
,
Christopher Batten
7
7/13/20
Applying BehavioralRTLIRPass to the cycle-level Component.
Hi Chris, Thanks for your answer. It was really helpful. And yes, I also felt manipulating CL models
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Applying BehavioralRTLIRPass to the cycle-level Component.
Hi Chris, Thanks for your answer. It was really helpful. And yes, I also felt manipulating CL models
7/13/20