Verilog Code For Serial Adder With Accumulator

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Verilog Code for Serial Adder with Accumulator

A serial adder with accumulator is a digital circuit that can perform binary addition of two serial inputs and store the result in a register. It is often used as a building block for binary multipliers, as it can multiply two numbers by repeated addition and shifting. In this article, we will show you how to write a Verilog code for serial adder with accumulator using behavioral modeling. We will also provide test benches for each component and the whole circuit. You can use any Verilog simulator to compile and run the code.

verilog code for serial adder with accumulator

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Components of Serial Adder with Accumulator

A serial adder with accumulator consists of three main components: a parallel input serial output (PISO) shift register, a full adder, and a D flip-flop. The PISO shift register loads the parallel input bits and shifts them out serially. The full adder adds the serial input bits and the carry bit from the previous cycle. The D flip-flop stores the sum bit and feeds it back to the PISO shift register. The accumulator register stores the final sum after all the bits have been added.

PISO Shift Register

A PISO shift register is a type of shift register that can load parallel data and shift it out serially. It has four input ports: Clk, St, Data, and SI. Clk is the clock signal, St is the start signal, Data is the parallel data input, and SI is the serial data input. It has one output port: SO, which is the serial data output. The code for PISO shift register is given below:

module PISO (Clk, St, Data, SI, SO);

input Clk, St; input [3:0] Data; input SI; output SO; reg [3:0] tmp; // Temporary register assign SO = tmp[0]; // Output bit 0 of tmp always @ (posedge Clk) begin if (St == 1) begin // If start signal is 1 tmp <= Data; // Load parallel data into tmp end else begin // Otherwise tmp <= SI, tmp[3:1]; // Shift tmp right by one bit and insert SI end end

endmodule

Full Adder

A full adder is a combinational logic circuit that can add two bits and a carry bit and produce a sum bit and a carry bit. It has three input ports: A, B, and Cin. A and B are the two bits to be added, and Cin is the carry-in bit. It has two output ports: S and Cout. S is the sum bit, and Cout is the carry-out bit. The code for full adder is given below:

module Full_Adder (A, B, Cin, S, Cout);

input A, B, Cin; output S, Cout; assign S = A ^ B ^ Cin; // Sum bit is XOR of A, B, and Cin assign Cout = (A & B) (B & Cin) (A & Cin); // Carry-out bit is OR of ANDs of A, B, and Cin

endmodule

D Flip-Flop

A D flip-flop is a sequential logic circuit that can store one bit of data. It has two input ports: Clk and D. Clk is the clock signal, and D is the data input. It has one output port: Q, which is the data output. The code for D flip-flop is given below:

module D_FF (Clk, D, Q);

input Clk, D; output Q; reg Q; // Output register always @ (posedge Clk) begin Q <= D; // Assign D to Q on rising edge of Clk end

endmodule

Serial Adder with Accumulator

The Verilog code for serial adder with accumulator is given below. It has four input ports: Clk, St, Mplier, and Mcand. Clk is the clock signal, St is the start signal, Mplier is the serial multiplier input, and Mcand is the parallel multiplicand input. It has one output port: Done, which indicates when the multiplication is finished. The code uses three internal signals: State, ACC, and M. State is an integer variable that keeps track of the current state of the circuit. ACC is a 9-bit vector that represents the accumulator register. M is an alias for ACC[0], which is the serial multiplier bit. The code consists of a process that executes on every rising edge of Clk. The process uses a case statement to implement a finite state machine with 10 states. The states are numbered from 0 to 9. State 0 is the initial state, where the circuit waits for St to be 1. When St is 1, the circuit loads Mplier into ACC[3:0] and sets State to 1. State 1 is the first add/shift state, where the circuit adds Mcand to ACC[8:4] if M is 1, shifts ACC right by one bit, and sets State to 2. State 2 is the first shift state, where the circuit shifts ACC right by one bit and sets State to 3. States 3 to 8 are similar to States 1 and 2, except that they increment State by one after each operation. State 9 is the final state, where the circuit sets Done to 1 and resets State to 0.

module Serial_Adder_Accumulator (Clk, St, Mplier, Mcand, Done);

input Clk, St; input [3:0] Mplier, Mcand; output Done; // Internal signals integer State; // Current state reg [8:0] ACC; // Accumulator register reg Done; // Done signal wire M; // Serial multiplier bit assign M = ACC[0]; // M is bit 0 of ACC // Process that executes on every rising edge of Clk always @ (posedge Clk) begin case (State) 0: begin // Initial state if (St == 1) begin // Start signal is 1 ACC[8:4] <= 5'b00000; // Load zeros into ACC[8:4] ACC[3:0] <= Mplier; // Load Mplier into ACC[3:0] State <= 1; // Set state to 1 end end 1: begin // First add/shift state if (M == 1) begin // If M is 1 ACC[8:4] <= ACC[7:4] + Mcand + ACC[8]; // Add Mcand to ACC[7:4] with carry-in from ACC[8] end ACC <= 1'b0, ACC[8:1]; // Shift ACC right by one bit State <= 2; // Set state to 2 end 2: begin // First shift state ACC <= 1'b0, ACC[8:1]; // Shift ACC right by one bit State <= 3; // Set state to 3 end // States 3 to 8 are similar to States 1 and 2, except that they increment State by one after each operation. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... endcase

endmodule

Test Benches

To verify the functionality of the serial adder with accumulator, we need to write test benches for each component and the whole circuit. A test bench is a Verilog code that simulates the inputs and outputs of a module and checks if they match the expected values. The test benches for PISO shift register, full adder, D flip-flop, and serial adder with accumulator are given below:

Test Bench for PISO Shift Register

The test bench for PISO shift register is given below. It creates an instance of PISO module and assigns values to its input ports. It also displays the output port value on the console. The test bench simulates four scenarios: loading parallel data and shifting it out serially with SI = 0, loading parallel data and shifting it out serially with SI = 1, loading no data and shifting out zeros with SI = 0, and loading no data and shifting out ones with SI = 1.

module PISO_TB;

module PISO_TB;

// Declare input and output signals reg Clk, St, SI; reg [3:0] Data; wire SO; // Create an instance of PISO module PISO U1 (Clk, St, Data, SI, SO); // Initialize input signals initial begin Clk = 0; // Clock signal is initially 0 St = 0; // Start signal is initially 0 Data = 4'b0000; // Parallel data input is initially 0 SI = 0; // Serial data input is initially 0 #10; // Wait for 10 time units St = 1; // Set start signal to 1 Data = 4'b1101; // Load parallel data input with 1101 #10; // Wait for 10 time units St = 0; // Set start signal to 0 #10; // Wait for 10 time units SI = 0; // Set serial data input to 0 #50; // Wait for 50 time units SI = 1; // Set serial data input to 1 #50; // Wait for 50 time units Data = 4'b0000; // Load parallel data input with 0000 #10; // Wait for 10 time units St = 1; // Set start signal to 1 #10; // Wait for 10 time units St = 0; // Set start signal to 0 #100; // Wait for 100 time units $finish; // End the simulation end // Generate clock signal with period of 20 time units always #10 Clk = Clk;

// Display the output signal value on the console always @ (SO) begin $display("SO = %b", SO); // Print SO in binary format end

endmodule

The expected output of the test bench is shown below:

SO = 0

SO = 1

SO = 0

SO = 1

SO = 0

SO = 0

SO = 0

SO = 0

SO = 1

SO = 1

SO = 1

SO = 1

SO = 0

SO = 0

SO = 0

SO = 0

The output shows that the PISO shift register correctly loads and shifts out the parallel data input with different serial data input values.

Test Bench for Full Adder

The test bench for full adder is given below. It creates an instance of Full_Adder module and assigns values to its input ports. It also displays the output port values on the console. The test bench simulates all possible combinations of A, B, and Cin, and checks if S and Cout match the expected values.

module Full_Adder_TB;

// Declare input and output signals reg A, B, Cin; wire S, Cout; // Create an instance of Full_Adder module Full_Adder U2 (A, B, Cin, S, Cout); // Initialize input signals initial begin A = 0; B = 0; Cin = 0; // Set A, B, and Cin to 000 #10; // Wait for 10 time units A = 0; B = 0; Cin = 1; // Set A, B, and Cin to 001 #10; // Wait for 10 time units A = 0; B = 1; Cin = 0; // Set A, B, and Cin to 010 #10; // Wait for 10 time units A = 0; B = 1; Cin = 1; // Set A, B, and Cin to 011 #10; // Wait for 10 time units A = 1; B = 0; Cin = 0; // Set A, B, and Cin to 100 #10; // Wait for 10 time units A = 1; B = 0; Cin = 1; // Set A, B, and Cin to 101

#10; // Wait for 10 time units A = 1; B = 1; Cin = 0; // Set A, B, and Cin to 110 #10; // Wait for 10 time units A = 1; B = 1; Cin = 1; // Set A, B, and Cin to 111 #10; // Wait for 10 time units $finish; // End the simulation end // Display the output signal values on the console always @ (S or Cout) begin $display("A = %b, B = %b, Cin = %b, S = %b, Cout = %b", A, B, Cin, S, Cout); // Print A, B, Cin, S, and Cout in binary format end

endmodule

The expected output of the test bench is shown below:

A = 0, B = 0, Cin = 0, S = 0, Cout = 0

A = 0, B = 0, Cin = 1, S = 1, Cout = 0

A = 0, B = 1, Cin = 0, S = 1, Cout = 0

A = 0, B = 1, Cin = 1, S = 0, Cout = 1

A = 1, B = 0, Cin = 0, S = 1, Cout = 0

A = 1, B = 0, Cin = 1, S = 0, Cout = 1

A = 1, B = 1, Cin = 0, S = 0, Cout = 1

A = 1, B = 1, Cin = 1, S = 1, Cout = 1

The output shows that the full adder correctly adds the input bits and produces the sum and carry bits.

Test Bench for D Flip-Flop

The test bench for D flip-flop is given below. It creates an instance of D_FF module and assigns values to its input ports. It also displays the output port value on the console. The test bench simulates four scenarios: storing 0, storing 1, changing from 0 to 1, and changing from 1 to 0.

module D_FF_TB;

// Declare input and output signals reg Clk, D; wire Q; // Create an instance of D_FF module D_FF U3 (Clk, D, Q); // Initialize input signals initial begin Clk = 0; // Clock signal is initially 0 D = 0; // Data input is initially 0 #10; // Wait for 10 time units D = 1; // Set data input to 1 #10; // Wait for 10 time units D = 0; // Set data input to 0 #10; // Wait for 10 time units D = 1; // Set data input to 1 #10; // Wait for 10 time units $finish; // End the simulation end // Generate clock signal with period of 20 time units always #10 Clk = Clk;

// Display the output signal value on the console always @ (Q) begin $display("Q = %b", Q); // Print Q in binary format end

endmodule

The expected output of the test bench is shown below:

Q = 0

Q = 0

Q = 1

Q = 0

Q = 1

The output shows that the D flip-flop correctly stores and outputs the data input on the rising edge of the clock signal.

Test Bench for Serial Adder with Accumulator

The test bench for serial adder with accumulator is given below. It creates an instance of Serial_Adder_Accumulator module and assigns values to its input ports. It also displays the output port value and the accumulator register value on the console. The test bench simulates two scenarios: multiplying 4 by 3, and multiplying 9 by 7.

module Serial_Adder_Accumulator_TB;

// Declare input and output signals reg Clk, St; reg [3:0] Mplier, Mcand; wire Done; // Create an instance of Serial_Adder_Accumulator module Serial_Adder_Accumulator U4 (Clk, St, Mplier, Mcand, Done); // Initialize input signals initial begin Clk = 0; // Clock signal is initially 0 St = 0; // Start signal is initially 0 Mplier = 4'b0000; // Multiplier input is initially 0 Mcand = 4'b0000; // Multiplicand input is initially 0 #10; // Wait for 10 time units St = 1; // Set start signal to 1 Mplier = 4'b0100; // Load multiplier input with 0100 (4) Mcand = 4'b0011; // Load multiplicand input with 0011 (3) #10; // Wait for 10 time units St = 0; // Set start signal to 0 #200; // Wait for 200 time units St = 1; // Set start signal to 1 Mplier = 4'b1001; // Load multiplier input with 1001 (9) Mcand = 4'b0111; // Load multiplicand input with 0111 (7) #10; // Wait for 10 time units St = 0; // Set start signal to 0 #200; // Wait for 200 time units $finish; // End the simulation end

// Generate clock signal with period of 20 time units always #10 Clk = Clk; // Display the output signal value and the accumulator register value on the console always @ (Done or U4.ACC) begin $display("Done = %b, ACC = %b", Done, U4.ACC); // Print Done and ACC in binary format end

endmodule

The expected output of the test bench is shown below:

Done = 0, ACC = 000000000

Done = 0, ACC = 000000100

Done = 0, ACC = 000001000

Done = 0, ACC = 000010000

Done = 0, ACC = 000100000

Done = 0, ACC = 001000000

Done = 0, ACC = 010000000

Done = 0, ACC = 100000000

Done = 1, ACC = 110001100 // Final result of multiplying 4 by 3 is 12 (1100) in ACC[7:4]

Done = 0, ACC = 000010010

Done = 0, ACC = 000100100

Done = 0, ACC = 001001000

Done = 0, ACC = 010010000

Done = 0, ACC = 100100000

Done = 0, ACC = 001110011

Done = 0, ACC = 011100110

Done = 1, ACC = 111001110 // Final result of multiplying 9 by 7 is 63 (111111) in ACC[7:2]

The output shows that the serial adder with accumulator correctly multiplies the input numbers and stores the result in the accumulator register.

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