PLP "JERUK" Development Board

[Wira Mulia]

Jeruk is a non-FPGA development board for PLP.

There are currently a development scratchpad site: http://wmulia.org/plp/jeruk/

and a Google Code website for firmware development: https://code.google.com/p/jeruk-fw/

The goal of the development board is to have an affordable hardware that can be used in computer-based classes that use the PLP framework. We have been using Nexys 2/3 boards to act as the CPU hardware, which is a bit pricey and a bit cumbersome to use.

Jeruk will have an emulation layer that will execute PLP CPU programs. fload protocol is already supported and PLPTool can download PLP CPU programs to the board's CPU main memory. Fritz is working on the emulator. Moving to a full MIPS based system is also an option with this board.

The board uses a PIC32MX270F256B processor (MIPS core).

There are currently 4 working JERUK boards in existence (2 with me, 1 with Fritz, and 1 is being used / developed on privately). I can mail a few unpopulated (or partly populated boards) if anyone is interested to develop / hack on the board.

-W