AOI plays a vital role in CMOS Image Sensor packaging. It ensures the highest quality by inspecting components for defects. ASMPT offers the groundbreaking AOI solution, the first sub-μm AOI machine for CMOS assembly. With advanced optics, it enables 2D and 3D wire bond inspection and features a patented FM cleaner for increased cleaning efficiency.
Arrays of Geiger-mode avalanche photodiodes (GmAPDs) are fabricated on a new type of engineered substrates with an epitaxial layer grown on silicon-on-insulator (SOI) wafers. The SOI-based structure facilitates rapid die-level bump bonding of the GmAPD array to a CMOS readout integrated circuit (ROIC) followed by substrate removal to make a backilluminated image sensor. To fabricate the engineered substrate, a commercial substrate with a 70-nm-thick SOI layer is implanted with BF2 ions to create a p+-doped passivation layer on the light illumination surface. Subsequently, a lightly p-doped silicon layer on which the GmAPD will be fabricated is grown using a homoepitaxy process. This approach allows for the use of chip-level hybridization to CMOS, avoiding the high cost and demanding wafer flatness and smoothness requirements of wafer-scale 3D integration processes. The new process yields cleaner wafers and allows for tighter control of detector layer thickness compared to the previous process. GmAPDs fabricated on 5-μm-thick epitaxial silicon have over 70% photon detection efficiency (PDE) when 532 nm light is focused into the center 3 μm of the device with an oxide layer that remains after substrate removal. With an anti-reflective coating, the PDE can be improved.
In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm 7 mm QFN package.
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