Msa Altair 5x Serial Number Location

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The S-100 bus also includes 8 interrupt signals. These are signals generatedby other devices when they need immediate attention from the CPU. Forexample (as we'll see later in this chapter), a keyboard mightgenerate an interrupt signal when a key is pressed. A short programrun by the 8080 can then determine what that key was and take someaction. The board containing the 8080 also generally includes a chipcalled the Intel 8214 Priority Interrupt Control Unit to handle theseinterrupts. When an interrupt occurs, this chip generates an interruptsignal to the 8080. When the 8080 acknowledges the interrupt, the chipprovides a RST (Restart) instruction that causes the microprocessor tosave the current program counter and branch to address 0000h, 0008h,0010h, 0018h, 0020h, 0028h, 0030h, or 0038h depending on theinterrupt.

Is each RST "hardwired" to a specific socket on the S-100 bus? In other words, if I plug the keyboard controller to the second socket, do I need to write my keyboard handler only at the specific memory address, for example 0008h? And if I change the keyboard controller slot to another bus socket, does the subroutine need to be moved to another RST address? Or maybe the mapping table can exist somewhere in the memory, but I don't see it in the Altair 8800 video.

I have looked this video - Altair 8800 - Interrupt Acknowledge Cycle and have few questions (I have read wikipedia Intel 8080 article, Altair 8800 Operator's manual, Charles Petzold "Code" and few article on the internet, like this and didn't found answer yet):

No, all it means that there are only 8 distinctive routines that can be called directly by issuing one of the RST instructions. It doesn't imply any relation to the number if interrupt serviceable devices or devices at all.

An interrupt controller (like 8259 *1) can issue one RST for all interrupts, having them all initiate the same routine and then be polled by the routine to check which is the one to be served. Or they can have separate. Or a mixture of both. It's up to the systems requirements (and what style the designer preferred).

Or, instead of an RST, a CALL can be delivered (*2). When the 8080 (or Z80 in Mode 0) senses a CALL opcode during an interrupt cycle it will issue two additional cycles to fetch the address to be used. Thus there can be as many different entrypoints as one wishes (*3)

To start with, there is no assumption if a device is represented by a single I/O address, or if it occupies several. A 8251 serial interface would occupy 4 I/O addresses, while a 16550 needs 8, and a 8250 can get alone with just two.

Next, a 'device' does not need to have an interrupt associated. It may or may not, depending on its purpose, structure and workings. This may even differ for the same type of device. For example a keyboard interface can be implemented interrupt driven - with issuing an interrupt for each keypress, or polled, where it' up to the CPU to look if a new keypress has occurred or not.

And last, an interrupt can be shared by two devices - like having a board with several 16550 sharing a single interrupt line, programmed to use the same RST. Resulting in one interrupt, one RST, two devices and 16 addresses.

No. The S100 bus (in actual use, not as with the original Altair) supports three interrupt lines: /RESET, /NMI and /INT which connect all slots in parallel. Ignoring /RESET and /NMI, there is only one line, thus there can not be a slot specific assignment (*4). It all depends on the CPU used, the interrupt mode used and programming of the interrupt controller used.

But as there is only one interrupt, it is the same for all devices. The routine is selected by what instruction is placed on the bus during an interrupt cycle by the interrupt controller. In case of an 8080/85, it will be one of 8 possible RST instructions inserted by the 8259 interrupt controller as well an arbitary CALL instruction. In case of a Z80 (Interrupt Mode 3) it might also be one of 128 vector numbers.

Now, if your question is about the 8 seperate interrupt lines usually called VI0..VI7, then again, they are shared between all boards and it's up to the system configuration if they get assigned to seperate boards (usually by jumpers) or get used by multiple - in both cases again, they can be used by one or more devices on these boards. Wellcome to the wonderful world of S100 bus configuration :))

Remember there is only one interrupt line on the CPU, so handling 8 lines from the bus means, that there must be an interrupt controller (8259) on the CPU board to encode and prioritize them. Otherwise they might be a bit hard to handle.

As said, the assignment of I/O addresses to 'devices' is arbitrary and decoded at each I/O board. (hopefully) The right board will respond to an address (if not we got a configuration error). The assignment is usually hard coded or can be selected from a predefined range by jumpers. On the software side it depends as usual on the software used. It may be hardcoded in the drivers (BIOS) or due some kind of configuration file.

Confused? Well, interrupt handling isn't the easyest lesson to learn when about a CPU, especially not with rather sophisticated mechanics like on the 8080/Z80 family. Just take your time an gnaw thru all the paper :)

*2 - IIRC, any instruction can be issued, but only RST and CALL do make sense under normal circumstances as they both do a proper subroutine invocation. Then again, with a careful design other instructions could be useful in the right situation.

*4 - Keep in mind, S100 is a simple parallel bus utilizing an undefined number of slots. None is prioritized or special in any way. Any card can be placed in any slot. Much like the PC bus system. In contrast the Apple II bus uses geographical addressing, meaning while each slot is electrical the same (lets ignore #0 and #7 for this), they will be seen on different address ranges by the CPU. That would be geographical addressing - which S100 is not.

A Restart Vector is actually a software interrupt and has nothing (at least not directly) to do with devices. The RST is rather something close to a CALL operation, or an interrupt triggered by software. The RST operation is only specific with regards to interrupts that it is the only opcode that generates a jump to a handler routine and occupies only one byte - Thus, external devices can push it onto the data bus during the interrupt acknowledge cycle of the CPU to cause a jump into an interrupt service routine. (The 8080 is pretty unique (simple?) in expecting interrupting devices to push an instruction onto the bus during the interrupt acknowledge cycle that will then be executed by the device)

Manassehkatz is correct about the bus. All components can see all bus activity. So each picks for itself which bus cycles to respond to; ordinarily IO accesses to a particular address or range of addresses.

That being said, the RSTs are then a natural choice, and I'd even be surprised if this isn't exactly why they exist. But if Intel had wanted to provide more RSTs then they'd have needed to remove other instructions to free up encodings and, in any case, encoding would have been tricky. 8080 instructions generally break down into two three-bit fields plus a two-bit part, and there are eight RSTs because one of those three-bit parts directly maps to the destination address.

This is one of the things that was extended on the Z80; one of its modes of operations allows external devices to supply an index into a vector lookup table rather than an instruction. So you're not alone in seeing a difficulty.

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