S.dump(); /* Function: _pocl_kernel_matvec_mult_ceWork Region: %pregion_for_entry.entry.i---%polly.merge_new_and_old Max Loop Depth: 1 Invariant Accesses: { } Context: [p_0, p_1, p_2] -> { : -2147483648 <= p_0 <= 2147483647 and -2147483648 <= p_1 <= 2147483647 and -2147483648 <= p_2 <= 2147483647 } Assumed Context: [p_0, p_1, p_2] -> { : } Invalid Context: [p_0, p_1, p_2] -> { : 4p_2 <= -134217729 - p_0 or p_0 <= -134217729 or p_0 >= 134217728 or 4p_2 >= 134217728 - p_0 or p_2 <= -33554433 or p_2 >= 33554432 or p_1 < 0 or (p_0 >= -1 and p_1 >= 134217729 + p_0) or (p_0 >= -1 and p_1 >= 2 + p_0 and 4p_2 >= 134217729 - p_1) } p0: %6 p1: %9 p2: %13 Arrays { <2 x i64> MemRef0[*]; // Element size 16 <2 x i64> MemRef1[*]; // Element size 16 float MemRef2[*]; // Element size 4 } Arrays (Bounds as pw_affs) { <2 x i64> MemRef0[*]; // Element size 16 <2 x i64> MemRef1[*]; // Element size 16 float MemRef2[*]; // Element size 4 } Alias Groups (2): [[ <[p_0, p_1, p_2] -> { MemRef0[(p_0 + 4p_2)] }, [p_0, p_1, p_2] -> { MemRef0[(p_1 + 4p_2)] : p_0 >= -1 and p_1 >= 2 + p_0; MemRef0[(1 + p_0 + 4p_2)] : p_1 <= 1 + p_0 or (p_0 <= -2 and p_1 >= 2 + p_0) }> <[p_0, p_1, p_2] -> { MemRef2[(p_0 + 4p_2)] }, [p_0, p_1, p_2] -> { MemRef2[(p_1 + 4p_2)] : p_0 >= -1 and p_1 >= 2 + p_0; MemRef2[(1 + p_0 + 4p_2)] : p_1 <= 1 + p_0 or (p_0 <= -2 and p_1 >= 2 + p_0) }> ]] [[ <[p_0, p_1, p_2] -> { MemRef1[(0)] }, [p_0, p_1, p_2] -> { MemRef1[(1)] }> <[p_0, p_1, p_2] -> { MemRef2[(p_0 + 4p_2)] }, [p_0, p_1, p_2] -> { MemRef2[(p_1 + 4p_2)] : p_0 >= -1 and p_1 >= 2 + p_0; MemRef2[(1 + p_0 + 4p_2)] : p_1 <= 1 + p_0 or (p_0 <= -2 and p_1 >= 2 + p_0) }> ]] Statements { Stmt0 Domain := [p_0, p_1, p_2] -> { Stmt0[i0] : p_0 >= -1 and 0 < i0 < -p_0 + p_1; Stmt0[0] : p_0 <= -2 or p_0 >= -1 }; Schedule := [p_0, p_1, p_2] -> { Stmt0[i0] -> [i0] : p_0 >= -1 and 0 < i0 < -p_0 + p_1; Stmt0[0] -> [0] }; ReadAccess := [Reduction Type: NONE] [Scalar: 0] [p_0, p_1, p_2] -> { Stmt0[i0] -> MemRef0[p_0 + 4p_2 + i0] }; ReadAccess := [Reduction Type: NONE] [Scalar: 0] [p_0, p_1, p_2] -> { Stmt0[i0] -> MemRef1[0] }; MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] [p_0, p_1, p_2] -> { Stmt0[i0] -> MemRef2[p_0 + 4p_2 + i0] }; Instructions { ... } } */ for (const ScopStmt &Stmt : S) { isl::set domain = Stmt.getDomain(); for (MemoryAccess *MA : Stmt) { if (!MA->isScalarKind()) { isl::set accessedMem; accessedMem = MA->getAccessRelation().intersect_domain(domain).range(); polly::simplify(accessedMem); accessedMem.dump(); // [p_0, p_1, p_2] -> { MemRef0[i0] : (p_0 >= -1 and i0 > p_0 + 4p_2 and i0 < p_1 + 4p_2) or i0 = p_0 + 4p_2 } isl::pw_multi_aff MinPMA, MaxPMA; isl::pw_aff MinPA, MaxPA; MinPMA = accessedMem.lexmin_pw_multi_aff(); MinPA = MinPMA.get_pw_aff(0); MinPA.coalesce().dump(); // [p_0, p_1, p_2] -> { [(p_0 + 4p_2)] } isl_ast_build *build = isl_ast_build_alloc(S.getIslCtx().get()); isl_ast_expr *minExpr = isl_ast_build_expr_from_pw_aff(build, MinPA.get()); llvm::Value *V = NodeBuilder.getExprBuilder().create(minExpr);
// /home/harry/llvm-project/polly/lib/CodeGen/IslExprBuilder.cpp:723: llvm::Value* polly::IslExprBuilder::createId(isl_ast_expr*): Assertion `IDToValue.count(Id) && "Identifier not found"' failed. } } }