Hi,
The term WPQ, or Write Pending Queue, refers to the queue of outstanding writes in the memory controller (part of the CPU chip). Each entry in the Write Pending Queue is a 64-byte cacheline and for PMem, the power supply must store enough energy to allow these queues to drain on power loss so that stores sitting in the WPQs can be considered persistent by software (known as the ADR feature, a platform feature required for supporting PMem).
I think what you are asking about isn't the WPQs, but instead the Write Data Buffers (WDBs) which are buffers located on the PMem device, used to hold data while the device is collecting adjacent cache lines to construct a full ECC block. We don't publish detailed information about the internal architecture of the PMem devices, but you can probably glean quite a bit of information about it by running tests and gathering stats using ipmwatch. The ipmwatch program is open source and you'll see a brief mention of the WDB in the documentation in the repo:
Note that one of the reasons the internal details are not published is that they may change significantly between generations, including the size and number of WDBs, as well as the algorithm for managing when data moves from a WDB to the media.
Hope that helps.
-andy